Variable buffer size descriptor fetching for a multi-queue direct memory access system
Descriptor fetch for a direct memory access system includes, in response to receiving a first data packet, fetching a plurality of descriptors including a first descriptor and a specified number of prefetched descriptors. The plurality of descriptors specify different buffer sizes. In response to processing each data packet, selectively replenishing the plurality of fetched descriptors to the specified number of prefetched descriptors.
1. A method of descriptor fetch for a direct memory access system, the method comprising:
in response to receiving a data packet, fetching a plurality of descriptors including a first descriptor and a specified number of prefetched descriptors;
wherein the plurality of descriptors specify different buffer sizes;
calculating an accumulated byte length for the different buffer sizes specified by the plurality of descriptors; and
in response to detecting that the accumulated byte length is greater than or equal to a size of the data packet, processing the data packet and replenishing the plurality of descriptors to the specified number of prefetched descriptors.
2. The method of claim 1 , further comprising:
in response to receiving subsequent data packets, fetching one descriptor per subsequent data packet.
3. The method of claim 2 , wherein the fetching one descriptor per subsequent data packet is performed in response to receiving each individual data packet.
4. The method of claim 1 , wherein the specified number of prefetched descriptors is programmable.
5. The method of claim 1 , wherein the specified number of prefetched descriptors is maintained during operation of the direct memory access system.
6. The method of claim 1 , wherein the replenishing the plurality of descriptors comprises:
in response to processing each data packet:
determining a number of the prefetched descriptors consumed in processing the data packet; and
prefetching a number of additional prefetched descriptors corresponding to the number of prefetched descriptors consumed in processing the data packet.
7. The method of claim 1 , further comprising:
dynamically switching between a variable size buffer descriptor mode and a low latency mode during operation.
8. The method of claim 7 , further comprising:
for each received descriptor:
comparing a length of a buffer specified by the descriptor with a threshold length; and
in response to determining that the length of the buffer is greater than or equal to the threshold length, adding the descriptor to a queue corresponding to the descriptor and enabling a low latency mode for the queue.
9. The method of claim 8 , further comprising:
dequeuing a descriptor from a selected queue;
determining a length of a buffer specified by the descriptor;
comparing the length of the buffer to the threshold length;
determining whether the low latency mode is enabled for the selected queue; and
in response to determining that the length of the buffer is greater than or equal to the threshold length and that the low latency mode is enabled for the selected queue, processing a data packet using the descriptor in the low latency mode.
10. The method of claim 8 , further comprising:
dequeuing a descriptor from a selected queue;
determining a length of a buffer specified by the descriptor;
comparing the length of the buffer to the threshold length;
determining whether the low latency mode is enabled for the selected queue; and
in response to determining that the length of the buffer is less than the threshold length or that the low latency mode is not enabled for the selected queue, processing a data packet using the variable size buffer descriptor mode.
11. A direct memory access system having a multi-queue stream circuit, the multi-queue stream circuit comprising:
a descriptor prefetch circuit configured to receive descriptor request events for a data packet, wherein the descriptor prefetch circuit includes:
a prefetch credit circuit configured to receive the descriptor request events and issue credit to a fetch circuit for a plurality of descriptors including a first descriptor and a specified number of prefetched descriptors; and
a prefetch cache configured to receive the plurality of descriptors, wherein the plurality of descriptors specify different buffer sizes;
wherein the prefetch cache is configured to calculate an accumulated byte length for the different buffer sizes specified by the plurality of descriptors; and
wherein the prefetch cache, in response to detecting that the accumulated byte length is greater than or equal to a size of the data packet, is configured to process the data packet and replenish the plurality of descriptors to the specified number of prefetched descriptors.
12. The direct memory access system of claim 11 , wherein, in response to receiving subsequent data packets, the prefetch credit circuit is configured to issue credit to the fetch circuit to fetch one descriptor per subsequent data packet.
13. The direct memory access system of claim 12 , wherein the fetching one descriptor per subsequent data packet is initiated by the prefetch credit circuit in response to receiving each individual data packet.
14. The direct memory access system of claim 11 , wherein the specified number of prefetched descriptors is programmable.
15. The direct memory access system of claim 11 , wherein the specified number of prefetched descriptors is maintained during operation of the direct memory access system.
16. The direct memory access system of claim 11 , wherein the prefetch cache is configured to, in response to processing each data packet:
determine a number of the prefetched descriptors consumed in processing the data packet; and
prefetch a number of additional prefetched descriptors corresponding to the number of prefetched descriptors consumed in processing the data packet.
17. A direct memory access system having a multi-queue stream circuit, the multi-queue stream circuit comprising:
a descriptor prefetch circuit configured to receive descriptor request events for a data packet and dynamically switch between a variable size buffer descriptor mode and a low latency mode during operation, wherein the descriptor prefetch circuit includes:
a prefetch credit circuit configured to receive the descriptor request events and issue credit to a fetch circuit for a plurality of descriptors including a first descriptor and a specified number of prefetched descriptors; and
a prefetch cache configured to receive the plurality of descriptors, wherein the plurality of descriptors specify different buffer sizes;
wherein the prefetch cache, in response to processing each data packet, is configured to replenish the plurality of descriptors to the specified number of prefetched descriptors; and
wherein the prefetch cache includes a main linked list comprising a descriptor queueing circuit, wherein the descriptor queueing circuit is configured to, for each descriptor received:
compare a length of a buffer specified by the descriptor with a threshold length; and
in response to determining that the length of the buffer is greater than or equal to the threshold length, add the descriptor to a queue corresponding to the descriptor and enable a low latency mode for the queue.
18. The direct memory access system of claim 17 , wherein the main linked list further comprises:
a descriptor dequeuing circuit configured to:
dequeue a descriptor from a selected queue;
determine a length of a buffer specified by the descriptor;
compare the length of the buffer to the threshold length;
determine whether the low latency mode is enabled for the selected queue; and
in response to determining that the length of the buffer is greater than or equal to the threshold length and that the low latency mode is enabled for the selected queue, process a data packet using the descriptor in the low latency mode.
19. The direct memory access system of claim 17 , wherein the main linked list further comprises:
a descriptor dequeuing circuit configured to:
dequeue a descriptor from a selected queue;
determine a length of a buffer specified by the descriptor;
compare the length of the buffer to the threshold length;
determine whether the low latency mode is enabled for the selected queue; and
in response to determining that the length of the buffer is less than the threshold length or that the low latency mode is not enabled for the selected queue, process a data packet using the variable size buffer descriptor mode.