Management of cache size
In response to a processor core exiting a low-power state, a cache is set to a minimum size so that fewer than all of the cache's entries are available to store data, thus reducing the cache's power consumption. Over time, the size of the cache can be increased to account for heightened processor activity, thus ensuring that processing efficiency is not significantly impacted by a reduced cache size. In some embodiments, the cache size is increased based on a measured processor performance metric, such as an eviction rate of the cache. In some embodiments, the cache size is increased at regular intervals until a maximum size is reached.
1. A method, comprising:
adjusting by a processor a size of a cache based on a performance metric of the processor by changing a number of ways of the cache available to store data, wherein adjusting the size of the cache comprises:
setting at the processor the size of the cache to a first size in response to a processor core of the processor exiting a low-power state; and
adjusting at the processor the size of the cache from the first size to a second size based on the performance metric reaching a first threshold.
2. The method of claim 1 , wherein adjusting the size of the cache further comprises:
adjusting the size of the cache from the second size to a third size based on the performance metric reaching a second threshold.
3. The method of claim 1 , wherein the performance metric comprises a number of cache lines evicted from the cache.
4. The method of claim 1 , wherein the performance metric comprises a rate at which cache lines are evicted from the cache.
5. The method of claim 4 , wherein the rate comprises a number of cache lines evicted from the cache per a number of micro-operations committed at an instruction pipeline of the processor.
6. The method of claim 1 , further comprising suspending adjustment of the size of the cache in response to a context switch at the processor indicating a processor core has switched from executing a first thread to executing a second thread.
7. The method of claim 1 , wherein the cache is shared between a first processor core and a second processor core.
8. A method, comprising:
identifying by a processor a frequency of the processor exiting a low-power state; and
periodically adjusting a size of a cache at the processor based on the frequency of the processor exiting the low-power state.
9. The method of claim 8 , further comprising suspending adjustment of the size of the cache in response to a context switch at the processor indicating a processor core has switched from executing a first thread to executing a second thread.
10. A processor, comprising:
a processor core;
a cache;
a performance monitor to measure a performance metric based on execution of instructions at the processor core; and
a cache controller to adjust a size the cache based on the performance metric by changing a number of ways of the cache available to store data, wherein the cache controller is to adjust the size of the cache by:
setting the size of cache to a first size in response to the processor core exiting a low-power state; and
adjusting the size of the cache from the first size to a second size based on the preformance metric reaching a first threshold.
11. The processor of claim 10 , wherein the cache controller is to further adjust the size of the cache by:
adjusting the size of the cache from the second size to a third size based on the performance metric reaching a second threshold.
12. The processor of claim 10 , wherein the performance metric comprises a number of cache lines evicted from the cache.
13. The processor of claim 10 , wherein the performance metric comprises a rate at which cache lines are evicted from the cache.
14. The processor of claim 13 , wherein the rate comprises a number of cache lines evicted from the cache per a number of micro-operations committed at an instruction pipeline of the processor core.
15. The processor of claim 10 , wherein the cache controller is to suspend adjustment of the size of the cache in response to a context switch at the processor indicating the processor core has switched from executing a first thread to executing a second thread.
16. A non-transitory computer readable medium storing code to adapt at least one computer system to perform a portion of a process to fabricate at least part of a processor, the processor comprising:
a processor core;
a cache;
a performance monitor to measure a performance metric based on execution of instructions at the processor core; and
a cache controller to adjust a size the cache based on the performance metric by changing a number of ways of the cache available to store data, wherein the cache controller is to adjust the size of the cache by:
setting the size of the cache to a first size in response to the processor core exiting a low-power state; and
adjusting the size of the cache from the first size to a second size based on the performance metric reaching a first threshold.
17. The computer readable medium of claim 16 , wherein the cache controller is to further adjust the size of the cache by:
adjusting the size of the cache from the second size to a third size based on the performance metric reaching a second threshold.
18. The computer readable medium of claim 16 , wherein the performance metric comprises a number of cache lines evicted from the cache.
19. The computer readable medium of claim 16 , wherein the performance metric comprises a rate at which cache lines are evicted from the cache.