Semiconductor device and data processing system selectively operating as one of a big endian or little endian system
The present invention is to provide a semiconductor device that can correctly switch endians on the outside even if the endian of a parallel interface is not recognized on the outside. The semiconductor device includes a switching circuit and a first register. The switching circuit switches between whether a parallel interface with the outside is to be used as a big endian or a little endian. A first register holds control data of the switching circuit. The switching circuit regards the parallel interface as the little endian when first predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register, and regards the parallel interface as the big endian when second predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register. Whatever the endian setting status, the control information can be correctly inputted without being influenced by the endian setting status.
1. A display controller driver disposed on one semiconductor substrate and adapted for use with a host device, the display controller driver comprising:
a command register adapted to store an endian setting command supplied from the host device; and
a control circuit configured to drive a display based on commands and data supplied from the host device,
wherein the control circuit interprets the commands and the data in either big endian or little endian based on a value of the command register,
wherein the command register is associated with an endian setting address, and
wherein the endian setting address includes a high-order bit portion and a low-order bit portion that are identical.
2. A display controller driver according to claim 1 ,
wherein the high-order bit portion of the value of the command register is 0000000X, where X is 0 when setting the little endian system, and where X is 1 when setting the big endian system, and
wherein the low-order bit portion of the value of the command register is 0000000Y, where Y is 0 when setting the little endian system, and where Y is 1 when setting the big endian system.
3. A display controller driver according to claim 1 ,
wherein the high-order bit portion of the endian setting address is 00000110, and
wherein the low-order bit portion of the endian setting address is 00000110.