IP Library Granted Patent US 10,199,501
Granted Patent B2
US 10,199,501 · App. 15/678,100 · Granted Feb 5, 2019

Method for forming semiconductor structure

Inventor: Chung-Yi Chiu (Tainan, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L29/7851H01L21/02532H01L21/32105H01L29/0649H01L29/1054H01L29/165H01L29/66431H01L29/66795
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Quick Facts
Patent No.
US 10,199,501
App. No.
15/678,100
Granted
Feb 5, 2019
Kind
B2
Abstract

A method for manufacturing a semiconductor structure includes the following steps. First, a semiconductor substrate including a first semiconductor material is provided. The semiconductor substrate includes a dielectric structure formed thereon, and the dielectric structure includes at least a recess formed therein. A first epitaxial layer is then formed in the recess. The first epitaxial layer includes at least a second semiconductor material that a lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. Subsequently, a thermal oxidation process is performed to the first epitaxial layer thereby forming a semiconductor layer at a bottom of the recess and a silicon oxide layer on the semiconductor layer. After removing the silicon oxide layer, a second epitaxial layer is formed on the semiconductor layer in the recess.

Claims (19)

1. A method for manufacturing a semiconductor structure comprising:

providing a semiconductor substrate comprising a first semiconductor material, the semiconductor substrate comprising a dielectric structure formed thereon, and the dielectric structure comprising at least a recess formed therein;

forming a first epitaxial layer in the recess, the first epitaxial layer comprising at least a second semiconductor material, and a lattice constant of the second semiconductor material being larger than a lattice constant of the first semiconductor material;

performing a thermal oxidation process to the first epitaxial layer to form a semiconductor layer in the semiconductor substrate and a silicon oxide layer formed on the semiconductor layer, wherein the semiconductor layer has an inverted trapezoid shape with a slanted edge surface extended directly under the dielectric structure, and a width of the inverted trapezoid shape is wider than a width of the recess;

removing the silicon oxide layer; and

forming a second epitaxial layer on the semiconductor layer in the recess.

2. The method for manufacturing the semiconductor structure according to claim 1 , wherein the first epitaxial layer further comprises the first semiconductor material.

3. The method for manufacturing the semiconductor structure according to claim 1 , wherein the first epitaxial layer comprises a thickness and the thickness is between 100 angstroms (Å) and 400Å.

4. The method for manufacturing the semiconductor structure according to claim 1 , wherein the thermal oxidation process comprises a process temperature and the process temperature is between 800° C and 1000°C.

5. The method for manufacturing the semiconductor structure according to claim 1 , wherein the second epitaxial layer comprises the first semiconductor material.

6. The method for manufacturing the semiconductor structure according to claim 5 , wherein the second epitaxial layer further comprises the second semiconductor material.

7. The method for manufacturing the semiconductor structure according to claim 6 , wherein a concentration of the second semiconductor material in the second epitaxial layer is between 20% and 80%.

8. The method for manufacturing the semiconductor structure according to claim 1 , further comprising removing a portion of the dielectric structure to form a fin in the recess.

9. The method for manufacturing the semiconductor structure according to claim 8 , wherein a top surface of the fin is higher than a top surface of the dielectric structure.

10. The method for manufacturing the semiconductor structure according to claim 8 , further comprising forming a gate layer on the fin.

11. The method for manufacturing the semiconductor structure according to claim 1 , wherein a bottom of the recess exposes a top surface of the substrate.

12. The method for manufacturing the semiconductor structure according to claim 11 , wherein the first epitaxial layer is directly formed on the top surface of the substrate and only filling a lower portion of the recess.

13. The method for manufacturing the semiconductor structure according to claim 11 , wherein the semiconductor layer is lower than the top surface of the substrate.

14. The method for manufacturing the semiconductor structure according to claim 1 , wherein the second epitaxial layer is directly formed on the semiconductor layer and completely fills up the recess.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2021
From: UNITED MICROELECTRONICS CORPORATION
To: MARLIN SEMICONDUCTOR LIMITED
Reel/Frame 056991/0292 →
Priority Claims (1)
TW 104136243 A · Nov 4, 2015 · national
Continuity (2)
Division 14954967 · Nov 30, 2015
Related Publication 20170345937A1 · Nov 30, 2017