IP Library › Granted Patent US 10,205,452
Granted Patent B2
US 10,205,452 · App. 15/681,457 · Granted Feb 12, 2019

Logic circuit, semiconductor device, electronic component, and electronic device

Inventor: Hikaru Tamura (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H03K19/0013G09G3/20G11C11/00G11C11/401G11C11/4094H01L27/10814H03K19/0966G11C7/1006G11C7/12
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Quick Facts
Patent No.
US 10,205,452
App. No.
15/681,457
Granted
Feb 12, 2019
Kind
B2
Abstract

A drive capability of a dynamic logic circuit is improved. A logic circuit includes a dynamic logic circuit, a first output node, a first transistor that is diode-connected, and a capacitor. The dynamic logic circuit includes a second output node. The first transistor and transistors in the dynamic logic circuit have an n-type conductivity or a p-type conductivity. The first output node is electrically connected to a first terminal of the capacitor, and the second output node is electrically connected to a second terminal of the capacitor. A first terminal of the first transistor is electrically connected to the first output node, and a first voltage is input to a second terminal of the first transistor.

Claims (66)

1. A logic circuit comprising:

a first wiring, a first transistor, and a first node, the first transistor connecting the first node to the first wiring;

a second wiring, a second transistor, and a second node, the second transistor connecting the second node to the second wiring;

a plurality of third transistors in a circuit connected between the first node and the second node;

a capacitor, a first terminal of the capacitor electrically connected to the first node; and

an output node electrically connected to a second terminal of the capacitor,

wherein the plurality of third transistors each include an oxide semiconductor comprising a channel formation region,

wherein the second transistor is configured to be on when the first transistor is off, and

wherein the second transistor is configured to be off when the first transistor is on.

2. The logic circuit according to claim 1 , wherein the plurality of third transistors are connected in series between the first node and the second node.

3. The logic circuit according to claim 2 , wherein the logic circuit is an AND logic circuit.

4. The logic circuit according to claim 1 , wherein the plurality of third transistors are connected in parallel between the first node and the second node.

5. The logic circuit according to claim 4 , wherein the logic circuit is an OR logic circuit.

6. The logic circuit according to claim 1 , wherein a dynamic logic circuit includes the first wiring, the second wiring, the first transistor, the second transistor, and the plurality of third transistors.

7. An electronic component comprising the logic circuit according to claim 1 , wherein a power supply voltage applied to the second wiring is greater than a power supply voltage applied to the first wiring.

8. A semiconductor device comprising:

a circuit array of a plurality of circuits; and

a peripheral circuit for driving the circuit array,

wherein the peripheral circuit includes the logic circuit according to claim 1 .

9. An electronic device comprising:

the logic circuit according to claim 1 ; and

at least one of a display device, a touch panel, a microphone, a speaker, an operation key, and a housing.

10. A logic circuit comprising:

a first wiring, a first transistor, and a first node, the first transistor connecting the first node to the first wiring;

a second wiring, a second transistor, and a second node, the second transistor connecting the second node to the second wiring;

a plurality of third transistors in a circuit connected between the first node and the second node; and

a capacitor electrically connected to the first node,

wherein the plurality of third transistors each include an oxide semiconductor comprising a channel formation region,

wherein the first transistor, the second transistor, and the plurality of third transistors have a same conductivity type,

wherein the second transistor is configured to be on when the first transistor is off, and

wherein the second transistor is configured to be off when the first transistor is on.

11. The logic circuit according to claim 10 , wherein the plurality of third transistors are connected in series between the first node and the second node.

12. The logic circuit according to claim 11 , wherein the logic circuit is an AND logic circuit.

13. The logic circuit according to claim 10 , wherein the plurality of third transistors are connected in parallel between the first node and the second node.

14. The logic circuit according to claim 13 , wherein the logic circuit is an OR logic circuit.

15. The logic circuit according to claim 10 , wherein a dynamic logic circuit includes the first wiring, the second wiring, the first transistor, the second transistor, and the plurality of third transistors.

16. An electronic component comprising the logic circuit according to claim 10 , wherein a power supply voltage applied to the second wiring is greater than a power supply voltage applied to the first wiring.

17. A semiconductor device comprising:

a circuit array of a plurality of circuits; and

a peripheral circuit for driving the circuit array,

wherein the peripheral circuit includes the logic circuit according to claim 10 .

18. An electronic device comprising:

the logic circuit according to claim 10 ; and

at least one of a display device, a touch panel, a microphone, a speaker, an operation key, and a housing.

19. A logic circuit comprising:

a first wiring, a first transistor, and a first node, the first transistor connecting the first node to the first wiring;

a second wiring, a second transistor, and a second node, the second transistor connecting the second node to the second wiring;

a plurality of third transistors in a circuit connected between the first node and the second node;

a capacitor electrically connected to the first node,

wherein the plurality of third transistors each include an oxide semiconductor comprising a channel formation region,

wherein the second transistor is configured to be on when the first transistor is off, and

wherein the second transistor is configured to be off when the first transistor is on.

20. The logic circuit according to claim 19 , wherein the plurality of third transistors are connected in series between the first node and the second node.

21. The logic circuit according to claim 20 , wherein the logic circuit is an AND logic circuit.

22. The logic circuit according to claim 19 , wherein the plurality of third transistors are connected in parallel between the first node and the second node.

23. The logic circuit according to claim 22 , wherein the logic circuit is an OR logic circuit.

24. The logic circuit according to claim 19 , wherein a dynamic logic circuit includes the first wiring, the second wiring, the first transistor, the second transistor, and the plurality of third transistors.

25. An electronic component comprising the logic circuit according to claim 19 , wherein a power supply voltage applied to the second wiring is greater than a power supply voltage applied to the first wiring.

26. A semiconductor device comprising:

a circuit array of a plurality of circuits; and

a peripheral circuit for driving the circuit array,

wherein the peripheral circuit includes the logic circuit according to claim 19 .

27. An electronic device comprising:

the logic circuit according to claim 19 ; and

at least one of a display device, a touch panel, a microphone, a speaker, an operation key, and a housing.

28. The logic circuit according to claim 1 , further comprising a fourth transistor electrically connected to the second terminal of the capacitor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 23, 2017
From: TAMURA, HIKARU
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 043925/0313 →
Priority Claims (1)
JP 2014-201056 · Sep 30, 2014 · national
Continuity (3)
Continuation 15262186 · Sep 12, 2016
Continuation 14864339 · Sep 24, 2015
Related Publication 20170346489A1 · Nov 30, 2017
Cited By (3)
US 12,232,368 US 12,362,732 US 12,575,132