IP Library › Granted Patent US 12,232,368
Granted Patent B2
US 12,232,368 · App. 17/742,842 · Granted Feb 18, 2025

Display device and electronic device

Inventors: Hideaki Shishido (Kanagawa, JP); Naoto Kusumoto (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H10K59/122G02F1/13306G06F3/0412G09G3/2092G09G3/3225G09G3/3233G09G3/3258G09G3/3648H01L29/7869H10K10/84H10K50/814H10K59/1213H10K59/128G02F2201/44G02F2203/02G06F3/041G06F2203/04103G09G2310/0291H01L27/1225H10K50/115H10K71/231
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Quick Facts
Patent No.
US 12,232,368
App. No.
17/742,842
Granted
Feb 18, 2025
Kind
B2
Abstract

A display device with a narrow bezel is provided. The display device includes a pixel circuit and a driver circuit which are provided on the same plane. The driver circuit includes a selection circuit and a buffer circuit. The selection circuit includes a first transistor. The buffer circuit includes a second transistor. The first transistor has a region overlapping with the second transistor. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor. One of a source and a drain of the second transistor is electrically connected to the pixel circuit.

Claims (20)

1. A display device comprising:

a pixel circuit and a driver circuit on a same plane as the pixel circuit,

wherein the driver circuit includes a selection circuit and a buffer circuit,

wherein the selection circuit includes a first transistor and the buffer circuit includes a second transistor,

wherein a channel width of the second transistor is larger than a channel width of the first transistor,

wherein an interlayer insulating film is provided over a channel formation region of the second transistor,

wherein a channel formation region of the first transistor is provided over the interlayer insulating film,

wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to a gate electrode of the second transistor through an opening provided in the interlayer insulating film,

wherein one of a source electrode and a drain electrode of the second transistor is electrically connected to a power supply line,

wherein the other of the source and the drain electrode of the second transistor is electrically connected to a gate line of the pixel circuit,

wherein, in a plan view, the power supply line has a region extending in a first direction,

wherein, in the plan view, the gate line has a region extending in the first direction,

wherein, in the plan view, the one of the source electrode and the drain electrode of the first transistor has a region extending in the first direction,

wherein, in the plan view, the other of the source electrode and the drain electrode of the first transistor has a region extending in the first direction,

wherein, in the plan view, a gate electrode of the first transistor has a region extending in a second direction,

wherein, in the plan view, a channel length direction of the second transistor is arranged in the second direction, and

wherein, in the plan view, the gate electrode of the second transistor has a region extending in the first direction.

2. The display device according to claim 1 , wherein a start pulse is input to the gate electrode of the first transistor.

3. The display device according to claim 1 , wherein the channel formation region of the first transistor includes an oxide semiconductor.

4. The display device according to claim 1 , wherein the channel formation region of the second transistor includes silicon.

Priority Claims (1)
JP 2016-142898 · Jul 21, 2016 · national
Continuity (3)
Continuation 16743220 · Jan 15, 2020
Continuation 15654108 · Jul 19, 2017
Related Publication 20220271109A1 · Aug 25, 2022
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