IP Library › Granted Patent US 11,189,647
Granted Patent B2
US 11,189,647 · App. 16/889,897 · Granted Nov 30, 2021

Liquid crystal display device and electronic device

Inventor: Atsushi Umezaki (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L27/124G02F1/1368G02F1/13306G02F1/13624G02F1/136286G09G3/20G09G3/3648G09G3/3677H01L21/84H01L27/12H01L27/1222H01L27/1225H01L27/156H01L27/3262H01L27/3276G02F1/136245G09G2300/04G09G2300/08G09G2310/0267G09G2310/0286G09G2310/08H01L29/78696
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Quick Facts
Patent No.
US 11,189,647
App. No.
16/889,897
Granted
Nov 30, 2021
Kind
B2
Abstract

To provide a circuit used for a shift register or the like. The basic configuration includes first to fourth transistors and four wirings. The power supply potential VDD is supplied to the first wiring and the power supply potential VSS is supplied to the second wiring. A binary digital signal is supplied to each of the third wiring and the fourth wiring. An H level of the digital signal is equal to the power supply potential VDD, and an L level of the digital signal is equal to the power supply potential VSS. There are four combinations of the potentials of the third wiring and the fourth wiring. Each of the first transistor to the fourth transistor can be turned off by any combination of the potentials. That is, since there is no transistor that is constantly on, deterioration of the characteristics of the transistors can be suppressed.

Claims (68)

1. A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a fifth transistor; and

a sixth transistor,

wherein a first terminal of the first transistor is electrically connected to a first wiring,

wherein a gate of the first transistor is electrically connected to a first terminal of the second transistor,

wherein a second terminal of the second transistor is directly connected to a gate of the second transistor,

wherein a first terminal of the third transistor is directly connected to a second terminal of the first transistor,

wherein a second terminal of the third transistor is electrically connected to a second wiring,

wherein a gate of the third transistor is directly connected to a gate of the fourth transistor,

wherein a first terminal of the fourth transistor is directly connected to the gate of the first transistor,

wherein a second terminal of the fourth transistor is electrically connected to the second wiring,

wherein a first terminal of the fifth transistor is directly connected to the second terminal of the first transistor,

wherein a second terminal of the fifth transistor is electrically connected to the second wiring,

wherein a first terminal of the sixth transistor is directly connected to the gate of the first transistor,

wherein a second terminal of the sixth transistor is electrically connected to the second wiring,

wherein a ratio of a channel width to a channel length of the fourth transistor is higher than a ratio of a channel width to a channel length of the second transistor, and

wherein a ratio of a channel width to a channel length of the sixth transistor is higher than the ratio of the channel width to the channel length of the second transistor.

2. The semiconductor device according to claim 1 ,

wherein the first terminal of the first transistor is directly connected to the first wiring.

3. The semiconductor device according to claim 1 ,

wherein the gate of the first transistor is directly connected to the first terminal of the second transistor.

4. The semiconductor device according to claim 1 ,

wherein the second terminal of the third transistor is directly connected to the second wiring.

5. The semiconductor device according to claim 1 ,

wherein the second terminal of the fourth transistor is directly connected to the second wiring.

6. The semiconductor device according to claim 1 ,

wherein the second terminal of the fifth transistor is directly connected to the second wiring.

7. The semiconductor device according to claim 1 ,

wherein the second terminal of the sixth transistor is directly connected to the second wiring.

8. A display device comprising:

a pixel portion; and

a driver circuit electrically connected to the pixel portion, the driver circuit comprising:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a fifth transistor; and

a sixth transistor,

wherein a first terminal of the first transistor is electrically connected to a first wiring,

wherein a gate of the first transistor is electrically connected to a first terminal of the second transistor,

wherein a second terminal of the second transistor is directly connected to a gate of the second transistor,

wherein a first terminal of the third transistor is directly connected to a second terminal of the first transistor,

wherein a second terminal of the third transistor is electrically connected to a second wiring,

wherein a gate of the third transistor is directly connected to a gate of the fourth transistor,

wherein a first terminal of the fourth transistor is directly connected to the gate of the first transistor,

wherein a second terminal of the fourth transistor is electrically connected to the second wiring,

wherein a first terminal of the fifth transistor is directly connected to the second terminal of the first transistor,

wherein a second terminal of the fifth transistor is electrically connected to the second wiring,

wherein a first terminal of the sixth transistor is directly connected to the gate of the first transistor,

wherein a second terminal of the sixth transistor is electrically connected to the second wiring,

wherein a ratio of a channel width to a channel length of the fourth transistor is higher than a ratio of a channel width to a channel length of the second transistor, and

wherein a ratio of a channel width to a channel length of the sixth transistor is higher than the ratio of the channel width to the channel length of the second transistor.

9. The display device according to claim 8 ,

wherein the first terminal of the first transistor is directly connected to the first wiring.

10. The display device according to claim 8 ,

wherein the gate of the first transistor is directly connected to the first terminal of the second transistor.

11. The display device according to claim 8 ,

wherein the second terminal of the third transistor is directly connected to the second wiring.

12. The display device according to claim 8 ,

wherein the second terminal of the fourth transistor is directly connected to the second wiring.

13. The display device according to claim 8 ,

wherein the second terminal of the fifth transistor is directly connected to the second wiring.

14. The display device according to claim 8 ,

wherein the second terminal of the sixth transistor is directly connected to the second wiring.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 2, 2020
From: UMEZAKI, ATSUSHI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 052810/0364 →
Priority Claims (1)
JP 2006-155472 · Jun 2, 2006 · national
Continuity (8)
Continuation 16420265 · May 23, 2019
Continuation 15954699 · Apr 17, 2018
Continuation 15279575 · Sep 29, 2016
Continuation 14967458 · Dec 14, 2015
Continuation 14510273 · Oct 9, 2014
Continuation 13675066 · Nov 13, 2012
Continuation 11747537 · May 11, 2007
Related Publication 20200295050A1 · Sep 17, 2020
Cited By (4)
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