Granted Patent B2

US 12,190,842 · App. 18/083,282 · Granted Jan 7, 2025

Inventor: Atsushi Umezaki (Kanagawa, JP)

Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

G09G3/3674G09G3/20G09G3/3688G11C19/28H03K3/356026H03K5/15066H03K5/15093G09G2310/0267G09G2310/0283G09G2310/0286G11C19/287H03K4/026

Abstract

Claims (23)

1. A semiconductor device comprising:

a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and a ninth transistor,

wherein one of a source and a drain of the first transistor is electrically connected to a clock signal line,

wherein the other of the source and the drain of the first transistor is electrically connected to an output terminal,

wherein one of a source and a drain of the second transistor is electrically connected to the output terminal,

wherein the other of the source and the drain of the second transistor is electrically connected to a first power supply line,

wherein one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor,

wherein the other of the source and the drain of the third transistor is electrically connected to a second power supply line,

wherein one of a source and a drain of the fourth transistor is electrically connected to the gate of the first transistor,

wherein one of a source and a drain of the fifth transistor is electrically connected to the gate of the first transistor,

wherein one of a source and a drain of the sixth transistor is electrically connected to a gate of the fourth transistor,

wherein the other of the source and the drain of the sixth transistor is electrically connected to a first signal line,

wherein a gate of the sixth transistor is electrically connected to the other of the source and the drain of the sixth transistor,

wherein one of a source and a drain of the seventh transistor is electrically connected to the gate of the fourth transistor,

wherein one of a source and a drain of the eighth transistor is electrically connected to a gate of the fifth transistor,

wherein the other of the source and the drain of the eighth transistor is electrically connected to a second signal line,

wherein a gate of the eighth transistor is electrically connected to the other of the source and the drain of the eighth transistor,

wherein one of a source and a drain of the ninth transistor is electrically connected to the gate of the fifth transistor,

wherein a gate of the ninth transistor is electrically connected to a gate of the seventh transistor,

wherein the fourth transistor is configured to control a potential of the gate of the first transistor,

wherein the fifth transistor is configured to control a potential of the gate of the first transistor,

wherein the seventh transistor is configured to control a potential of the gate of the fourth transistor, and

wherein the ninth transistor is configured to control a potential of the gate of the fifth transistor.

Priority Claims (1)

Continuity (4)

References Cited (179)