Display device
By applying an AC pulse to a gate of a transistor which easily deteriorates, a shift in threshold voltage of the transistor is suppressed. However, in a case where amorphous silicon is used for a semiconductor layer of a transistor, the occurrence of a shift in threshold voltage naturally becomes a problem for a transistor which constitutes a part of circuit that generates an AC pulse. A shift in threshold voltage of a transistor which easily deteriorates and a shift in threshold voltage of a turned-on transistor are suppressed by signal input to a gate electrode of the transistor which easily deteriorates through the turned-on transistor. In other words, a structure for applying an AC pulse to a gate electrode of a transistor which easily deteriorates through a transistor to a gate electrode of which a high potential (VDD) is applied, is included.
1. A display device comprising:
a pixel; and
a scan line driver circuit comprising:
a first transistor;
a second transistor;
a third transistor;
a fourth transistor;
a fifth transistor; and
a sixth transistor,
wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to a first wiring,
wherein the other of the source electrode and the drain electrode of the first transistor is electrically connected to a first scan line,
wherein one of a source electrode and a drain electrode of the second transistor is electrically connected to a second wiring,
wherein the other of the source electrode and the drain electrode of the second transistor is electrically connected to the first scan line,
wherein one of a source electrode and a drain electrode of the third transistor is electrically connected to a gate electrode of the first transistor,
wherein one of a source electrode and a drain electrode of the fourth transistor is electrically connected to the second wiring,
wherein the other of the source electrode and the drain electrode of the fourth transistor is electrically connected to the gate electrode of the first transistor,
wherein a gate electrode of the fourth transistor is electrically connected to a second scan line,
wherein one of a source electrode and a drain electrode of the fifth transistor is electrically connected to a third wiring to which an AC pulse is supplied,
wherein the other of the source electrode and the drain electrode of the fifth transistor is electrically connected to a gate electrode of the second transistor,
wherein one of a source electrode and a drain electrode of the sixth transistor is electrically connected to a fourth wiring,
wherein the other of the source electrode and the drain electrode of the sixth transistor is electrically connected to the gate electrode of the second transistor,
wherein a gate electrode of the sixth transistor is electrically connected to the gate electrode of the first transistor,
wherein the third transistor is configured to control a potential of the gate electrode of the first transistor such that the first transistor is turned on,
wherein the fourth transistor is configured to control the potential of the gate electrode of the first transistor such that the first transistor is turned off,
wherein the fifth transistor is configured to control a potential of the gate electrode of the second transistor such that the second transistor is turned on,
wherein the sixth transistor is configured to control the potential of the gate electrode of the second transistor such that the second transistor is turned off, and
wherein the pixel is electrically connected to the first scan line.
2. The display device according to claim 1 ,
wherein a conductive layer comprises the one of the source electrode and the drain electrode of the second transistor, and
wherein the conductive layer comprises the one of the source electrode and the drain electrode of the fourth transistor.
3. A display device comprising:
a pixel; and
a scan line driver circuit comprising:
a first transistor;
a second transistor;
a third transistor;
a fourth transistor;
a fifth transistor; and
a sixth transistor,
wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to a first wiring,
wherein the other of the source electrode and the drain electrode of the first transistor is electrically connected to a first scan line,
wherein one of a source electrode and a drain electrode of the second transistor is electrically connected to a second wiring,
wherein the other of the source electrode and the drain electrode of the second transistor is electrically connected to the first scan line,
wherein one of a source electrode and a drain electrode of the third transistor is electrically connected to a gate electrode of the first transistor,
wherein one of a source electrode and a drain electrode of the fourth transistor is electrically connected to the second wiring,
wherein the other of the source electrode and the drain electrode of the fourth transistor is electrically connected to the gate electrode of the first transistor,
wherein a gate electrode of the fourth transistor is electrically connected to a second scan line,
wherein one of a source electrode and a drain electrode of the fifth transistor is electrically connected to a third wiring to which an AC pulse is supplied,
wherein the other of the source electrode and the drain electrode of the fifth transistor is electrically connected to a gate electrode of the second transistor,
wherein one of a source electrode and a drain electrode of the sixth transistor is electrically connected to a fourth wiring,
wherein the other of the source electrode and the drain electrode of the sixth transistor is electrically connected to the gate electrode of the second transistor,
wherein a gate electrode of the sixth transistor is electrically connected to the gate electrode of the first transistor,
wherein the third transistor is configured to control a potential of the gate electrode of the first transistor such that the first transistor is turned on,
wherein the fourth transistor is configured to control the potential of the gate electrode of the first transistor such that the first transistor is turned off,
wherein the fifth transistor is configured to control a potential of the gate electrode of the second transistor such that the second transistor is turned on,
wherein the sixth transistor is configured to control the potential of the gate electrode of the second transistor such that the second transistor is turned off,
wherein a values of ratio W/L of a channel length L and a channel width W of the first transistor is greater than a value of ratio W/L of a channel length L and a channel width W of the second transistor,
wherein the values of ratio W/L of the channel length L and the channel width W of the first transistor is greater than a value of ratio W/L of a channel length L and a channel width W of the third transistor,
wherein the values of ratio W/L of the channel length L and the channel width W of the first transistor is greater than a value of ratio W/L of a channel length L and a channel width W of the fourth transistor,
wherein the values of ratio W/L of the channel length L and the channel width W of the first transistor is greater than a value of ratio W/L of a channel length L and a channel width W of the fifth transistor,
wherein the values of ratio W/L of the channel length L and the channel width W of the first transistor is greater than a value of ratio W/L of a channel length L and a channel width W of the sixth transistor,
wherein the values of ratio W/L of the channel length L and the channel width W of the sixth transistor is greater than the value of ratio W/L of the channel length L and the channel width W of the fifth transistor, and
wherein the pixel is electrically connected to the first scan line.
4. The display device according to claim 3 ,
wherein a conductive layer comprises the one of the source electrode and the drain electrode of the second transistor, and
wherein the conductive layer comprises the one of the source electrode and the drain electrode of the fourth transistor.
5. The display device according to claim 3 ,
wherein a first conductive layer comprises the other of the source electrode and the drain electrode of the first transistor,
wherein a second conductive layer comprises the other of the source electrode and the drain electrode of the second transistor, and
wherein the first conductive layer is electrically connected to the second conductive layer via a third conductive layer.
6. The display device according to claim 3 ,
wherein the pixel comprises a gate electrode, a gate insulating film over the gate electrode, a semiconductor layer over the gate insulating film, a source electrode and a drain electrode over the semiconductor layer, a pixel electrode electrically connected to one of the source electrode and the drain electrode, an insulating film over the source electrode, the drain electrode and the pixel electrode and a liquid crystal layer over the insulating film,
wherein the pixel electrode comprises a region in contact with a top surface of the one of the source electrode and the drain electrode and a region in contact with a top surface of the gate insulating film, and
wherein the insulating film comprises a region in contact with the top surface of the gate insulating film, a region in contact with a top surface of the semiconductor layer, a region in contact with a top surface of the source electrode, a region in contact with a top surface of the drain electrode and a region in contact with a top surface of the pixel electrode.
7. A display device comprising:
a pixel; and
a scan line driver circuit comprising:
a first transistor;
a second transistor;
a third transistor;
a fourth transistor;
a fifth transistor; and
a sixth transistor,
wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to a first wiring,
wherein the other of the source electrode and the drain electrode of the first transistor is electrically connected to a first scan line,
wherein one of a source electrode and a drain electrode of the second transistor is electrically connected to a second wiring,
wherein the other of the source electrode and the drain electrode of the second transistor is electrically connected to the first scan line,
wherein one of a source electrode and a drain electrode of the third transistor is electrically connected to a gate electrode of the first transistor,
wherein one of a source electrode and a drain electrode of the fourth transistor is electrically connected to the second wiring,
wherein the other of the source electrode and the drain electrode of the fourth transistor is electrically connected to the gate electrode of the first transistor,
wherein a gate electrode of the fourth transistor is electrically connected to a second scan line,
wherein one of a source electrode and a drain electrode of the fifth transistor is electrically connected to a third wiring to which an AC pulse is supplied,
wherein the other of the source electrode and the drain electrode of the fifth transistor is electrically connected to a gate electrode of the second transistor,
wherein one of a source electrode and a drain electrode of the sixth transistor is electrically connected to a fourth wiring,
wherein the other of the source electrode and the drain electrode of the sixth transistor is electrically connected to the gate electrode of the second transistor,
wherein a gate electrode of the sixth transistor is electrically connected to the gate electrode of the first transistor,
wherein the third transistor is configured to control a potential of the gate electrode of the first transistor such that the first transistor is turned on,
wherein the fourth transistor is configured to control the potential of the gate electrode of the first transistor such that the first transistor is turned off,
wherein the fifth transistor is configured to control a potential of the gate electrode of the second transistor such that the second transistor is turned on,
wherein the sixth transistor is configured to control the potential of the gate electrode of the second transistor such that the second transistor is turned off,
wherein a first conductive layer comprises the other of the source electrode and the drain electrode of the first transistor,
wherein a second conductive layer comprises the other of the source electrode and the drain electrode of the second transistor,
wherein the first conductive layer is electrically connected to the second conductive layer via a third conductive layer, and
wherein the pixel is electrically connected to the first scan line.
8. The display device according to claim 7 ,
wherein a fourth conductive layer comprises the one of the source electrode and the drain electrode of the second transistor, and
wherein the fourth conductive layer comprises the one of the source electrode and the drain electrode of the fourth transistor.
9. The display device according to claim 7 ,
wherein the pixel comprises a gate electrode, a gate insulating film over the gate electrode, a semiconductor layer over the gate insulating film, a source electrode and a drain electrode over the semiconductor layer, a pixel electrode electrically connected to one of the source electrode and the drain electrode, an insulating film over the source electrode, the drain electrode and the pixel electrode and a liquid crystal layer over the insulating film,
wherein the pixel electrode comprises a region in contact with a top surface of the one of the source electrode and the drain electrode and a region in contact with a top surface of the gate insulating film, and
wherein the insulating film comprises a region in contact with the top surface of the gate insulating film, a region in contact with a top surface of the semiconductor layer, a region in contact with a top surface of the source electrode, a region in contact with a top surface of the drain electrode and a region in contact with a top surface of the pixel electrode.
10. A display device comprising:
a pixel; and
a scan line driver circuit comprising:
a first transistor;
a second transistor;
a third transistor;
a fourth transistor;
a fifth transistor; and
a sixth transistor,
wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to a first wiring,
wherein the other of the source electrode and the drain electrode of the first transistor is electrically connected to a first scan line,
wherein one of a source electrode and a drain electrode of the second transistor is electrically connected to a second wiring,
wherein the other of the source electrode and the drain electrode of the second transistor is electrically connected to the first scan line,
wherein one of a source electrode and a drain electrode of the third transistor is electrically connected to a gate electrode of the first transistor,
wherein one of a source electrode and a drain electrode of the fourth transistor is electrically connected to the second wiring,
wherein the other of the source electrode and the drain electrode of the fourth transistor is electrically connected to the gate electrode of the first transistor,
wherein a gate electrode of the fourth transistor is electrically connected to a second scan line,
wherein one of a source electrode and a drain electrode of the fifth transistor is electrically connected to a third wiring to which an AC pulse is supplied,
wherein the other of the source electrode and the drain electrode of the fifth transistor is electrically connected to a gate electrode of the second transistor,
wherein one of a source electrode and a drain electrode of the sixth transistor is electrically connected to a fourth wiring,
wherein the other of the source electrode and the drain electrode of the sixth transistor is electrically connected to the gate electrode of the second transistor,
wherein a gate electrode of the sixth transistor is electrically connected to the gate electrode of the first transistor,
wherein the third transistor is configured to control a potential of the gate electrode of the first transistor such that the first transistor is turned on,
wherein the fourth transistor is configured to control the potential of the gate electrode of the first transistor such that the first transistor is turned off,
wherein the fifth transistor is configured to control a potential of the gate electrode of the second transistor such that the second transistor is turned on,
wherein the sixth transistor is configured to control the potential of the gate electrode of the second transistor such that the second transistor is turned off,
wherein the pixel comprises a gate electrode, a gate insulating film over the gate electrode, a semiconductor layer over the gate insulating film, a source electrode and a drain electrode over the semiconductor layer, a pixel electrode electrically connected to one of the source electrode and the drain electrode, an insulating film over the source electrode, the drain electrode and the pixel electrode and a liquid crystal layer over the insulating film,
wherein the pixel electrode comprises a region in contact with a top surface of the one of the source electrode and the drain electrode and a region in contact with a top surface of the gate insulating film,
wherein the insulating film comprises a region in contact with the top surface of the gate insulating film, a region in contact with a top surface of the semiconductor layer, a region in contact with a top surface of the source electrode, a region in contact with a top surface of the drain electrode and a region in contact with a top surface of the pixel electrode, and
wherein the pixel is electrically connected to the first scan line.
11. The display device according to claim 10 ,
wherein a conductive layer comprises the one of the source electrode and the drain electrode of the second transistor, and
wherein the conductive layer comprises the one of the source electrode and the drain electrode of the fourth transistor.