IP Library › Granted Patent US 10,606,140
Granted Patent B2
US 10,606,140 · App. 16/438,666 · Granted Mar 31, 2020

Liquid crystal display device

Inventor: Atsushi Umezaki (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
G02F1/136286G02F1/1368G02F1/13306G02F1/13452G02F1/136213G09G3/342G09G3/3674G09G3/3677G09G3/3685G11C19/28H01L27/06H01L27/124H01L27/1222H01L27/1225H01L27/1255H01L27/15H01L27/156H01L29/247H01L29/78693G02F1/1393G02F1/133753G02F2001/133622G02F2202/103G09G3/3655G09G2300/0426G09G2300/0452G09G2310/024G09G2310/0286G09G2310/08G09G2320/0252G09G2330/021H01L21/67167H01L27/3211H01L27/3213H01L27/3216H01L27/3248H01L27/3258H01L27/3262H01L27/3265H01L27/3276H01L51/5246H01L51/56H01L2251/5307H01L2251/5315H01L2251/5323
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Quick Facts
Patent No.
US 10,606,140
App. No.
16/438,666
Granted
Mar 31, 2020
Kind
B2
Abstract

A first transistor, a second transistor, a third transistor, a fourth transistor are provided. In the first transistor, a first terminal is electrically connected to a first wiring; a second terminal is electrically connected to a gate terminal of the second transistor; a gate terminal is electrically connected to a fifth wiring. In the second transistor, a first terminal is electrically connected to a third wiring; a second terminal is electrically connected to a sixth wiring. In the third transistor, a first terminal is electrically connected to a second wiring; a second terminal is electrically connected to the gate terminal of the second transistor; a gate terminal is electrically connected to a fourth wiring. In the fourth transistor, a first terminal is electrically connected to the second wiring; a second terminal is electrically connected to the sixth wiring; a gate terminal is connected to the fourth wiring.

Claims (152)

1. A semiconductor device comprising:

first to seventh transistors;

wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,

wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,

wherein the one of the source and the drain of the third transistor is electrically connected to a gate of the first transistor,

wherein the one of the source and the drain of the third transistor is electrically connected to a gate of the seventh transistor,

wherein one of a source and a drain of the fifth transistor is electrically connected to a gate of the fourth transistor,

wherein one of a source and a drain of the sixth transistor is electrically connected to one of a source and a drain of the seventh transistor,

wherein the one of the source and the drain of the sixth transistor is electrically connected to a gate of the fifth transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to a first wring,

wherein the other of the source and the drain of the fourth transistor is electrically connected to the first wring,

wherein the other of the source and the drain of the seventh transistor is electrically connected to the first wring,

wherein the other of the source and the drain of the fifth transistor is electrically connected to a second wring,

wherein a gate of the second transistor is electrically connected to the second wring, and

wherein the other of the source and the drain of the sixth transistor is electrically connected to a gate of the sixth transistor.

2. A semiconductor device comprising:

first to ninth transistors;

wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,

wherein the one of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the eighth transistor,

wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,

wherein the one of the source and the drain of the third transistor is electrically connected to a gate of the first transistor,

wherein the one of the source and the drain of the third transistor is electrically connected to a gate of the seventh transistor,

wherein the one of the source and the drain of the third transistor is electrically connected to a gate of the ninth transistor,

wherein one of a source and a drain of the fifth transistor is electrically connected to a gate of the fourth transistor,

wherein one of a source and a drain of the sixth transistor is electrically connected to one of a source and a drain of the seventh transistor,

wherein the one of the source and the drain of the sixth transistor is electrically connected to a gate of the fifth transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to a first wring,

wherein the other of the source and the drain of the fourth transistor is electrically connected to the first wring,

wherein the other of the source and the drain of the seventh transistor is electrically connected to the first wring,

wherein the other of the source and the drain of the eighth transistor is electrically connected to the first wring,

wherein the other of the source and the drain of the ninth transistor is electrically connected to the first wring,

wherein the other of the source and the drain of the fifth transistor is electrically connected to a second wring,

wherein a gate of the second transistor is electrically connected to the second wring,

wherein the other of the source and the drain of the sixth transistor is electrically connected to a gate of the sixth transistor,

wherein a gate of the eighth transistor is electrically connected to a third wring, and

wherein a gate of the ninth transistor is electrically connected to the third wring.

3. A semiconductor device comprising:

first to seventh transistors;

wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,

wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,

wherein the one of the source and the drain of the third transistor is electrically connected to a gate of the first transistor,

wherein the one of the source and the drain of the third transistor is electrically connected to a gate of the seventh transistor,

wherein one of a source and a drain of the fifth transistor is electrically connected to a gate of the fourth transistor,

wherein one of a source and a drain of the sixth transistor is electrically connected to one of a source and a drain of the seventh transistor,

wherein the one of the source and the drain of the sixth transistor is electrically connected to a gate of the fifth transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to a first wring,

wherein the other of the source and the drain of the fourth transistor is electrically connected to the first wring,

wherein the other of the source and the drain of the seventh transistor is electrically connected to the first wring,

wherein the other of the source and the drain of the fifth transistor is electrically connected to a second wring,

wherein a gate of the second transistor is electrically connected to the second wring,

wherein the other of the source and the drain of the sixth transistor is electrically connected to a gate of the sixth transistor, and

wherein the other of the source and the drain of the third transistor is electrically connected to a gate of the third transistor.

4. A semiconductor device comprising:

first to ninth transistors;

wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,

wherein the one of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the eighth transistor,

wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,

wherein the one of the source and the drain of the third transistor is electrically connected to a gate of the first transistor,

wherein the one of the source and the drain of the third transistor is electrically connected to a gate of the seventh transistor,

wherein the one of the source and the drain of the third transistor is electrically connected to a gate of the ninth transistor,

wherein one of a source and a drain of the fifth transistor is electrically connected to a gate of the fourth transistor,

wherein one of a source and a drain of the sixth transistor is electrically connected to one of a source and a drain of the seventh transistor,

wherein the one of the source and the drain of the sixth transistor is electrically connected to a gate of the fifth transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to a first wring,

wherein the other of the source and the drain of the fourth transistor is electrically connected to the first wring,

wherein the other of the source and the drain of the seventh transistor is electrically connected to the first wring,

wherein the other of the source and the drain of the eighth transistor is electrically connected to the first wring,

wherein the other of the source and the drain of the ninth transistor is electrically connected to the first wring,

wherein the other of the source and the drain of the fifth transistor is electrically connected to a second wring,

wherein a gate of the second transistor is electrically connected to the second wring,

wherein the other of the source and the drain of the sixth transistor is electrically connected to a gate of the sixth transistor,

wherein a gate of the eighth transistor is electrically connected to a third wring,

wherein a gate of the ninth transistor is electrically connected to the third wring, and

wherein the other of the source and the drain of the third transistor is electrically connected to a gate of the third transistor.

5. A semiconductor device comprising:

first to seventh transistors;

wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,

wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,

wherein the one of the source and the drain of the third transistor is electrically connected to a gate of the first transistor,

wherein the one of the source and the drain of the third transistor is electrically connected to a gate of the seventh transistor,

wherein one of a source and a drain of the fifth transistor is electrically connected to a gate of the fourth transistor,

wherein one of a source and a drain of the sixth transistor is electrically connected to one of a source and a drain of the seventh transistor,

wherein the one of the source and the drain of the sixth transistor is electrically connected to a gate of the fifth transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to a first wring,

wherein the other of the source and the drain of the fourth transistor is electrically connected to the first wring,

wherein the other of the source and the drain of the seventh transistor is electrically connected to the first wring,

wherein the other of the source and the drain of the fifth transistor is electrically connected to a second wring,

wherein a gate of the second transistor is electrically connected to the second wring,

wherein the other of the source and the drain of the sixth transistor is electrically connected to a gate of the sixth transistor, and

wherein a channel width of the first transistor is larger than a channel width of the third transistor.

6. A semiconductor device comprising:

first to ninth transistors;

wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,

wherein the one of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the eighth transistor,

wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,

wherein the one of the source and the drain of the third transistor is electrically connected to a gate of the first transistor,

wherein the one of the source and the drain of the third transistor is electrically connected to a gate of the seventh transistor,

wherein the one of the source and the drain of the third transistor is electrically connected to a gate of the ninth transistor,

wherein one of a source and a drain of the fifth transistor is electrically connected to a gate of the fourth transistor,

wherein one of a source and a drain of the sixth transistor is electrically connected to one of a source and a drain of the seventh transistor,

wherein the one of the source and the drain of the sixth transistor is electrically connected to a gate of the fifth transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to a first wring,

wherein the other of the source and the drain of the fourth transistor is electrically connected to the first wring,

wherein the other of the source and the drain of the seventh transistor is electrically connected to the first wring,

wherein the other of the source and the drain of the eighth transistor is electrically connected to the first wring,

wherein the other of the source and the drain of the ninth transistor is electrically connected to the first wring,

wherein the other of the source and the drain of the fifth transistor is electrically connected to a second wring,

wherein a gate of the second transistor is electrically connected to the second wring,

wherein the other of the source and the drain of the sixth transistor is electrically connected to a gate of the sixth transistor,

wherein a gate of the eighth transistor is electrically connected to a third wring,

wherein a gate of the ninth transistor is electrically connected to the third wring, and

wherein a channel width of the first transistor is larger than a channel width of the third transistor.

7. A semiconductor device comprising:

first to seventh transistors;

wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,

wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,

wherein the one of the source and the drain of the third transistor is electrically connected to a gate of the first transistor,

wherein the one of the source and the drain of the third transistor is electrically connected to a gate of the seventh transistor,

wherein one of a source and a drain of the fifth transistor is electrically connected to a gate of the fourth transistor,

wherein one of a source and a drain of the sixth transistor is electrically connected to one of a source and a drain of the seventh transistor,

wherein the one of the source and the drain of the sixth transistor is electrically connected to a gate of the fifth transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to a first wring,

wherein the other of the source and the drain of the fourth transistor is electrically connected to the first wring,

wherein the other of the source and the drain of the seventh transistor is electrically connected to the first wring,

wherein the other of the source and the drain of the fifth transistor is electrically connected to a second wring,

wherein a gate of the second transistor is electrically connected to the second wring,

wherein the other of the source and the drain of the sixth transistor is electrically connected to a gate of the sixth transistor,

wherein the other of the source and the drain of the third transistor is electrically connected to a gate of the third transistor, and

wherein a channel width of the first transistor is larger than a channel width of the third transistor.

8. A semiconductor device comprising:

first to ninth transistors;

wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,

wherein the one of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the eighth transistor,

wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,

wherein the one of the source and the drain of the third transistor is electrically connected to a gate of the first transistor,

wherein the one of the source and the drain of the third transistor is electrically connected to a gate of the seventh transistor,

wherein the one of the source and the drain of the third transistor is electrically connected to a gate of the ninth transistor,

wherein one of a source and a drain of the fifth transistor is electrically connected to a gate of the fourth transistor,

wherein one of a source and a drain of the sixth transistor is electrically connected to one of a source and a drain of the seventh transistor,

wherein the one of the source and the drain of the sixth transistor is electrically connected to a gate of the fifth transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to a first wring,

wherein the other of the source and the drain of the fourth transistor is electrically connected to the first wring,

wherein the other of the source and the drain of the seventh transistor is electrically connected to the first wring,

wherein the other of the source and the drain of the eighth transistor is electrically connected to the first wring,

wherein the other of the source and the drain of the ninth transistor is electrically connected to the first wring,

wherein the other of the source and the drain of the fifth transistor is electrically connected to a second wring,

wherein a gate of the second transistor is electrically connected to the second wring,

wherein the other of the source and the drain of the sixth transistor is electrically connected to a gate of the sixth transistor,

wherein a gate of the eighth transistor is electrically connected to a third wring,

wherein a gate of the ninth transistor is electrically connected to the third wring,

wherein the other of the source and the drain of the third transistor is electrically connected to a gate of the third transistor, and

wherein a channel width of the first transistor is larger than a channel width of the third transistor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 12, 2019
From: UMEZAKI, ATSUSHI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 049447/0285 →
Priority Claims (1)
JP 2006-236392 · Aug 31, 2006 · national
Continuity (10)
Continuation 16143059 · Sep 26, 2018
Continuation 15624987 · Jun 16, 2017
Continuation 15140577 · Apr 28, 2016
Continuation 14934243 · Nov 6, 2015
Continuation 14168058 · Jan 30, 2014
Continuation 13904147 · May 29, 2013
Continuation 13307131 · Nov 30, 2011
Continuation 12977556 · Dec 23, 2010
Division 11845415 · Aug 27, 2007
Related Publication 20190310529A1 · Oct 10, 2019
Cited By (8)
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