Liquid crystal display device

1. A display device comprising:

a pixel region provided over a first substrate; and

a scan line driver circuit provided over the first substrate,

wherein the scan line driver circuit includes

a first transistor, a second transistor, a third transistor, and a fourth transistor,

wherein the first, second, third, and fourth transistors are the same polarity,

wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor, the other of the source and the drain of the first transistor is electrically connected to a first wiring to which at least a first clock signal is input, and a gate of the first transistor is electrically connected to one of a source and a drain of the third transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to a second wiring to which at least a first potential is input, and a gate of the second transistor is electrically connected to a gate of the fourth transistor,

wherein the one of the source and the drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,

wherein the first wiring has a first region and the second wiring has a second region, and

wherein a width of the first region of the first wiring is larger than a width of the second region of the second wiring.

2. A display module including:

the display device according to claim 1 ; and

a flexible printed circuit.

3. An electronic device including:

the display module according to claim 2 ; and

at least one of an operation switch, a battery, an antenna, and a housing.

4. A display device comprising:

a pixel region provided over a first substrate; and

a scan line driver circuit provided over the first substrate,

wherein the scan line driver circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor,

wherein the first, second, third, and fourth transistors are the same polarity,

wherein a channel width of the first transistor is larger than a channel width of each of the second transistor, the third transistor, and the fourth transistor,

wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor, the other of the source and the drain of the first transistor is electrically connected to a first wiring to which at least a first clock signal is input, and a gate of the first transistor is electrically connected to one of a source and a drain of the third transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to a second wiring to which at least a first potential is input, and a gate of the second transistor is electrically connected to a gate of the fourth transistor,

wherein the one of the source and the drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,

wherein the first wiring has a first region and the second wiring has a second region, and

wherein a width of the first region of the first wiring is larger than a width of the second region of the second wiring.

5. A display module including:

the display device according to claim 4 ; and

a flexible printed circuit.

6. An electronic device including:

the display module according to claim 5 ; and

at least one of an operation switch, a battery, an antenna, and a housing.

7. A display device comprising:

a pixel region provided over a first substrate; and

a scan line driver circuit provided over the first substrate,

wherein the scan line driver circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor,

wherein the first, second, third, fourth, and fifth transistors are the same polarity,

wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor and one of a source and a drain of the fifth transistor, the other of the source and the drain of the first transistor is electrically connected to a first wiring to which at least a first clock signal is input, and a gate of the first transistor is electrically connected to one of a source and a drain of the third transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to a second wiring to which at least a first potential is input, and a gate of the second transistor is electrically connected to a gate of the fourth transistor,

wherein the one of the source and the drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,

wherein a gate of the fifth transistor is electrically connected to a third wiring to which at least a second clock signal is input,

wherein the first wiring has a first region, the second wiring has a second region, and the third wiring has a third region,

wherein a width of the first region of the first wiring is larger than a width of the second region of the second wiring, and

wherein a width of the third region of the third wiring is larger than the width of the second region of the second wiring.

8. A display module including:

the display device according to claim 7 ; and

a flexible printed circuit.

9. An electronic device including:

the display module according to claim 8 ; and

at least one of an operation switch, a battery, an antenna, and a housing.

10. A display device comprising:

a pixel region provided over a first substrate; and

a scan line driver circuit provided over the first substrate,

wherein the scan line driver circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor,

wherein the first, second, third, fourth, and fifth transistors are the same polarity,

wherein a channel width of the first transistor is larger than a channel width of each of the second transistor, the third transistor, and the fourth transistor,

wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor and one of a source and a drain of the fifth transistor, the other of the source and the drain of the first transistor is electrically connected to a first wiring to which at least a first clock signal is input, and a gate of the first transistor is electrically connected to one of a source and a drain of the third transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to a second wiring to which at least a first potential is input, and a gate of the second transistor is electrically connected to a gate of the fourth transistor,

wherein the one of the source and the drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,

wherein a gate of the fifth transistor is electrically connected to a third wiring to which at least a second clock signal is input,

wherein the first wiring has a first region, the second wiring has a second region, and the third wiring has a third region,

wherein a width of the first region of the first wiring is larger than a width of the second region of the second wiring, and

wherein a width of the third region of the third wiring is larger than the width of the second region of the second wiring.

11. A display module including:

the display device according to claim 10 ; and

a flexible printed circuit.

12. An electronic device including:

the display module according to claim 11 ; and

at least one of an operation switch, a battery, an antenna, and a housing.

13. A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor; and

a fourth transistor,

wherein the first, second, third, and fourth transistors are the same polarity,

wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor, the other of the source and the drain of the first transistor is electrically connected to a first wiring to which at least a first clock signal is input, and a gate of the first transistor is electrically connected to one of a source and a drain of the third transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to a second wiring to which at least a first potential is input, and a gate of the second transistor is electrically connected to a gate of the fourth transistor,

wherein the one of the source and the drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,

wherein the first wiring has a first region and the second wiring has a second region, and

wherein a width of the first region of the first wiring is larger than a width of the second region of the second wiring.

14. The semiconductor device according to claim 13 , wherein the first, second, third, and fourth transistors are included in a shift register in the semiconductor device.

15. A display module including:

the semiconductor device according to claim 13 ; and

a flexible printed circuit.

16. An electronic device including:

the display module according to claim 15 ; and

at least one of an operation switch, a battery, an antenna, and a housing.

17. A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor; and

a fourth transistor,

wherein the first, second, third, and fourth transistors are the same polarity,

wherein a channel width of the first transistor is larger than a channel width of each of the second transistor, the third transistor, and the fourth transistor,

wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor, the other of the source and the drain of the first transistor is electrically connected to a first wiring to which at least a first clock signal is input, and a gate of the first transistor is electrically connected to one of a source and a drain of the third transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to a second wiring to which at least a first potential is input, and a gate of the second transistor is electrically connected to a gate of the fourth transistor,

wherein the one of the source and the drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,

wherein the first wiring has a first region and the second wiring has a second region, and

wherein a width of the first region of the first wiring is larger than a width of the second region of the second wiring.

18. The semiconductor device according to claim 17 , wherein the first, second, third, and fourth transistors are included in a shift register in the semiconductor device.

19. A display module including:

the semiconductor device according to claim 17 ; and

a flexible printed circuit.

20. An electronic device including:

the display module according to claim 19 ; and

at least one of an operation switch, a battery, an antenna, and a housing.

21. A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor; and

a fifth transistor,

wherein the first, second, third, fourth, and fifth transistors are the same polarity,

wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor and one of a source and a drain of the fifth transistor, the other of the source and the drain of the first transistor is electrically connected to a first wiring to which at least a first clock signal is input, and a gate of the first transistor is electrically connected to one of a source and a drain of the third transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to a second wiring to which at least a first potential is input, and a gate of the second transistor is electrically connected to a gate of the fourth transistor,

wherein the one of the source and the drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,

wherein a gate of the fifth transistor is electrically connected to a third wiring to which at least a second clock signal is input,

wherein the first wiring has a first region, the second wiring has a second region, and the third wiring has a third region,

wherein a width of the first region of the first wiring is larger than a width of the second region of the second wiring, and

wherein a width of the third region of the third wiring is larger than the width of the second region of the second wiring.

22. The semiconductor device according to claim 21 , wherein the first, second, third, fourth, and fifth transistors are included in a shift register in the semiconductor device.

23. A display module including:

the semiconductor device according to claim 21 ; and

a flexible printed circuit.

24. An electronic device including:

the display module according to claim 23 ; and

at least one of an operation switch, a battery, an antenna, and a housing.

25. A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor; and

a fifth transistor,

wherein the first, second, third, fourth, and fifth transistors are the same polarity,

wherein a channel width of the first transistor is larger than a channel width of each of the second transistor, the third transistor, and the fourth transistor,

wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor and one of a source and a drain of the fifth transistor, the other of the source and the drain of the first transistor is electrically connected to a first wiring to which at least a first clock signal is input, and a gate of the first transistor is electrically connected to one of a source and a drain of the third transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to a second wiring to which at least a first potential is input, and a gate of the second transistor is electrically connected to a gate of the fourth transistor,

wherein the one of the source and the drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,

wherein a gate of the fifth transistor is electrically connected to a third wiring to which at least a second clock signal is input, wherein the first wiring has a first region, the second wiring has a second region, and the third wiring has a third region,

wherein a width of the first region of the first wiring is larger than a width of the second region of the second wiring, and

wherein a width of the third region of the third wiring is larger than the width of the second region of the second wiring.

26. The semiconductor device according to claim 25 , wherein the first, second, third, fourth, and fifth transistors are included in a shift register in the semiconductor device.

27. A display module including:

the semiconductor device according to claim 25 ; and

a flexible printed circuit.

28. An electronic device including:

the display module according to claim 27 ; and

at least one of an operation switch, a battery, an antenna, and a housing.