Granted Patent B2

US 12,477,781 · App. 18/736,777 · Granted Nov 18, 2025

Inventors: Hidekazu Miyairi (Kanagawa, JP); Takeshi Osada (Kanagawa, JP); Shunpei Yamazaki (Tokyo, JP)

Assignee: Semiconductor Energy Laboratory Co., Ltd.

H10D30/6755H01L21/02565H01L21/47635H01L21/477H10D30/6715H10D30/6729H10D30/673H10D30/6733H10D30/6734H10D62/80H10D64/512H10D64/62H10D86/021H10D86/423H10D86/471H10D86/60H10D99/00

Abstract

Claims (77)

1 . A semiconductor device comprising:

a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor,

wherein one of a source and a drain of the first transistor is electrically connected to a gate line,

wherein the other of the source and the drain of the first transistor is electrically connected to a clock signal line,

wherein one of a source and a drain of the second transistor is electrically connected to the gate line,

wherein the other of the source and the drain of the second transistor is electrically connected to a first power supply line,

wherein one of a source and a drain of the third transistor is electrically connected to a gate electrode of the second transistor,

wherein the other of the source and the drain of the third transistor is electrically connected to the first power supply line,

wherein a gate electrode of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,

wherein the other of the source and the drain of the fourth transistor is electrically connected to the first power supply line,

wherein a gate electrode of the fourth transistor is electrically connected to the gate electrode of the second transistor,

wherein one of a source and a drain of the fifth transistor is electrically connected to the gate electrode of the third transistor,

wherein the other of the source and the drain of the fifth transistor is electrically connected to a second power supply line,

wherein a gate electrode of the fifth transistor is electrically connected to a first signal line,

wherein the semiconductor device further comprises:

a first conductive layer comprising a region which functions a gate electrode of the first transistor;

a second conductive layer comprising a region which functions as the one of the source and the drain of the third transistor; and

a third conductive layer comprising a region which functions as the gate electrode of the fourth transistor, and

wherein the first conductive layer is electrically connected to the third conductive layer through the second conductive layer.

2 . The semiconductor device according to claim 1 , further comprising:

a fourth conductive layer comprising a region which functions as the gate electrode of the third transistor,

wherein the second conductive layer comprises a region overlapping with the fourth conductive layer in a region where the second conductive layer does not overlap with a semiconductor layer included in the third transistor.

3 . The semiconductor device according to claim 1 ,

wherein, when the first power supply line is in a conduction state with at least the gate electrode of the first transistor and the gate electrode of the third transistor through a channel formation region of the fourth transistor, a potential of the first power supply line is input to at least the gate electrode of the first transistor and the gate electrode of the third transistor through the channel formation region of the fourth transistor, and

wherein, when the second power supply line is in a conduction state with at least the gate electrode of the first transistor and the gate electrode of the third transistor through a channel formation region of the fifth transistor, a potential of the second power supply line is input to at least the gate electrode of the first transistor and the gate electrode of the third transistor through the channel formation region of the fifth transistor.

4 . The semiconductor device according to claim 1 , further comprising a sixth transistor,

wherein one of a source and a drain of the sixth transistor is electrically connected to a gate electrode of the third transistor,

wherein the other of the source and the drain of the sixth transistor is electrically connected to the first power supply line, and

wherein a gate electrode of the sixth transistor is electrically connected to a second signal line.

5 . The semiconductor device according to claim 4 ,

wherein, when the first power supply line is in a conduction state with at least the gate electrode of the first transistor and the gate electrode of the third transistor through a channel formation region of the sixth transistor, a potential of the first power supply line is input to at least the gate electrode of the first transistor and the gate electrode of the third transistor through the channel formation region of the sixth transistor.

6 . The semiconductor device according to claim 1 ,

wherein at least one of the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor comprises an oxide semiconductor in a channel formation region.

7 . The semiconductor device according to claim 1 ,

wherein the second conductive layer comprises a region positioned over the first conductive layer and a region positioned over the third conductive layer.

8 . A semiconductor device comprising:

a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor,

wherein one of a source and a drain of the first transistor is electrically connected to a gate line,

wherein the other of the source and the drain of the first transistor is electrically connected to a clock signal line,

wherein one of a source and a drain of the second transistor is electrically connected to the gate line,

wherein one of a source and a drain of the third transistor is electrically connected to a gate electrode of the second transistor,

wherein the other of the source and the drain of the third transistor is electrically connected to a power supply line,

wherein a gate electrode of the third transistor is electrically connected to a first signal line,

wherein one of a source and a drain of the fourth transistor is electrically connected to a gate electrode of the first transistor,

wherein the other of the source and the drain of the fourth transistor is electrically connected to the power supply line,

wherein a gate electrode of the fourth transistor is electrically connected to the gate electrode of the second transistor,

wherein one of a source and a drain of the fifth transistor is electrically connected to the gate electrode of the first transistor,

wherein a gate electrode of the fifth transistor is electrically connected to the first signal line,

wherein one of a source and a drain of the sixth transistor is electrically connected to the gate electrode of the second transistor,

wherein the other of the source and the drain of the sixth transistor is electrically connected to a first wiring,

wherein a gate electrode of the sixth transistor is electrically connected to the first wiring,

wherein the semiconductor device further comprises:

a first conductive layer comprising a region which functions as a gate electrode of the second transistor;

a second conductive layer comprising a region which functions as the one of the source and the drain of the third transistor;

a third conductive layer comprising a region which functions as the gate electrode of the fourth transistor; and

a fourth conductive layer comprising a region which functions as the gate electrode of the third transistor,

wherein the first conductive layer is electrically connected to the third conductive layer through the second conductive layer, and

wherein the second conductive layer overlaps with the fourth conductive layer in a region where the second conductive layer does not overlap with a semiconductor layer of the third transistor.

9 . The semiconductor device according to claim 8 ,

wherein, when the other of the source and the drain of the second transistor is in a conduction state with the gate line at least through a channel formation region of the second transistor, a potential that makes the gate line low is input to the gate line at least through the channel formation region of the second transistor, and

wherein when the other of the source and the drain of the fifth transistor is in a conduction state with the gate electrode of the first transistor at least through a channel formation region of the fifth transistor, a potential that makes the first transistor on is input to the gate electrode of the first transistor through at least the channel formation region of the fifth transistor.

10 . The semiconductor device according to claim 8 , further comprising:

a seventh transistor,

wherein one of a source and a drain of the seventh transistor is electrically connected to the gate electrode of the first transistor,

wherein the other of the source and the drain of the seventh transistor is electrically connected to the power supply line, and

wherein the gate electrode of the seventh transistor is electrically connected to a second signal line.

11 . The semiconductor device according to claim 8 ,

wherein at least one of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor comprises an oxide semiconductor in a channel formation region.

12 . The semiconductor device according to claim 8 , further comprising:

a seventh transistor,

wherein one of a source and a drain of the seventh transistor is electrically connected to the gate electrode of the first transistor,

wherein the other of the source and the drain of the seventh transistor is electrically connected to the power supply line,

wherein the gate electrode of the seventh transistor is electrically connected to a second signal line, and

wherein at least one of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor comprises an oxide semiconductor in a channel formation region.

13 . The semiconductor device according to claim 8 ,

wherein the second conductive layer comprises a region positioned over the first conductive layer, and

wherein the second conductive layer comprises a region positioned over the third conductive layer.

Assignments (1)

Priority Claims (1)

Continuity (10)

References Cited (400)