Air gap and air spacer pinch off

1. A method for forming a semiconductor device, the method comprising:

forming a gate electrode on a substrate and over a channel region of a semiconductor fin;

forming a contact on a doped region of the substrate in a manner that leaves a space between the contact and the gate electrode defining a trench, wherein the doped region and the gate electrode extend upward from the substrate from a same plane;

forming a first dielectric layer over the electrode and the contact such that the first dielectric layer partially fills the trench; and

forming a second dielectric layer over the first dielectric layer such that an air spacer is formed in the trench between the electrode and the contact.

2. The method of claim 1 , wherein forming the first dielectric layer comprises conformally depositing the first dielectric layer over the electrode and the contact.

3. The method of claim 2 , wherein the first dielectric layer comprises MnSiOx, MnSiCOx, or MnSiCONx.

4. The method of claim 1 , wherein forming the second dielectric layer comprises nonconformally depositing the second dielectric layer over the trench to pinch off an opening of the trench.

5. The method of claim 4 , wherein the second dielectric layer comprises a low-k dielectric, a nitride, a silicon nitride (SiN), a silicon carbonitride (SiCN), a silicon oxygen carbonitride (SiOCN), or a silicoboron carbonitride (SiBCN).

6. The method of claim 1 , further comprising forming a plurality of adjacent gate electrodes on the substrate, each gate electrode of the plurality of adjacent gate electrodes formed over a respective channel region of a respective semiconductor fin.

7. The method of claim 6 , further comprising forming a contact between each pair of adjacent gate electrodes, each contact formed on a doped region of the substrate, each contact separated from a first gate electrode of each pair of adjacent gate electrodes by a first space and a second gate electrode of each pair of adjacent gate electrodes by a second space.

8. The method of claim 7 , wherein each space defines a trench.

9. A method for forming a semiconductor device, the method comprising:

forming a gate electrode on a substrate and over a channel region of a semiconductor fin;

forming a contact on a doped region of the substrate, wherein the doped region and the gate electrode extend upward from the substrate from a same plane;

removing portions of an interlayer dielectric between the gate electrode and the contact in a manner that leaves a space between the contact and the gate electrode;

conformally depositing a first dielectric layer over the gate electrode and the contact such that the first dielectric layer partially fills the space; and

nonconformally depositing a second dielectric layer over the first dielectric layer such that an air spacer is formed between the gate electrode and the contact.

10. The method of claim 9 , wherein the first dielectric layer comprises MnSiOx, MnSiCOx, or MnSiCONx.

11. The method of claim 9 , wherein nonconformally depositing the second dielectric layer pinches off an opening of the space.

12. The method of claim 9 , wherein the second dielectric layer comprises a low-k dielectric, a nitride, a silicon nitride (SiN), a silicon carbonitride (SiCN), a silicon oxygen carbonitride (SiOCN), or a silicoboron carbonitride (SiBCN).

13. The method of claim 9 , further comprising forming a plurality of adjacent gate electrodes on the substrate, each gate electrode of the plurality of adjacent gate electrodes over a respective channel region of a respective semiconductor fin.

14. The method of claim 13 , further comprising forming a contact between each pair of adjacent gate electrodes, each contact formed on a doped region of the substrate, each contact separated from a first gate electrode of each pair of adjacent gate electrodes by a first space and a second gate electrode of each pair of adjacent gate electrodes by a second space.

15. The method of claim 14 , wherein each space defines a trench.

16. A method for forming a semiconductor device, the method comprising:

forming a gate electrode on a substrate and over a channel region of a semiconductor fin;

forming a contact on a doped region of the substrate;

removing portions of an interlayer dielectric between the gate electrode and the contact;

conformally depositing a first dielectric layer over the gate electrode, the contact, and remaining portions of the interlayer dielectric, the first dielectric layer comprising MnSiOx, MnSiCOx, or MnSiCONx; and

nonconformally depositing a second dielectric layer over the first dielectric layer such that an air spacer is formed between the gate electrode and the contact, the second dielectric layer comprising a silicon carbonitride (SiCN), a silicon oxygen carbonitride (SiOCN), or a silicoboron carbonitride (SiBCN).

17. The method of claim 16 , further comprising forming a plurality of adjacent gate electrodes on the substrate, each gate electrode of the plurality of adjacent gate electrodes formed over a respective channel region of a respective semiconductor fin.

18. The method of claim 17 , further comprising forming a contact between each pair of adjacent gate electrodes, each contact formed on a doped region of the substrate, each contact separated from a first gate electrode of each pair of adjacent gate electrodes by a first air spacer and a second gate electrode of each pair of adjacent gate electrodes by a second air spacer.

19. The method of claim 16 , wherein conformally depositing the first dielectric layer further comprises chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), evaporation, physical vapor deposition (PVD), or chemical solution deposition.

20. The method of claim 19 , further comprising conformally depositing the first dielectric layer to a thickness of about 2 nm to about 8 nm.