Integrated semiconductor device having isolation structure for reducing noise
View Patent ↗An integrated semiconductor device includes a first transistor and a second transistor formed on a semiconductor substrate, and an isolation structure located adjacent to the transistors, including deep trenches, trapping regions formed between the deep trenches, and trench bottom doping regions formed at the end of each of the deep trenches, wherein each of the trapping regions includes a buried layer, a well region formed on the buried layer, and a highly doped region formed on the well region.
1. An integrated semiconductor device, comprising:
a first transistor and a second transistor sensitive to noise formed on a semiconductor substrate; and
an isolation structure located adjacent to the transistors, comprising
deep trenches,
trapping regions formed between the deep trenches, and
trench bottom doping regions formed on an end of each of the deep trenches,
wherein each of the trapping regions comprises
a buried layer,
a well region formed on the buried layer, and
a highly doped region formed on the well region.
2. The integrated semiconductor device of claim 1 ,
wherein the deep trenches comprise a first trench, a second trench, a third trench, and a fourth trench formed spaced apart from each other,
wherein the trapping regions comprise
a first trapping region formed between the first trench and the second trench,
a second trapping region formed between the second trench and the third trench, and
a third trapping region formed between the third trench and the fourth trench, and
wherein the first trapping region and the third trapping region have a same depth.
3. The integrated semiconductor device of claim 1 , wherein a trench bottom doping region contacts two trenches.
4. The integrated semiconductor device of claim 1 ,
wherein the first transistor comprises either one or both of a Radio Frequency (RF) Complementary Metal-Oxide-Semiconductor (CMOS) transistor and a Hall sensor.
5. The integrated semiconductor device of claim 4 ,
wherein the RF CMOS transistor comprises:
a buried layer of a first conductivity type formed on the semiconductor substrate;
a first well region of a second conductivity type and a second well region of the first conductivity type formed on the buried layer;
a first RF MOSFET formed on the first well region; and
a second RF MOSFET formed on the second well region.
6. The integrated semiconductor device of claim 5 ,
wherein the buried layer of the RF CMOS transistor directly contacts one of the deep trenches.
7. The integrated semiconductor device of claim 4 ,
wherein the Hall sensor comprises:
a sensing region of a first conductivity type formed on the substrate;
highly doped regions of the first conductivity type formed on the sensing region and located apart from each other;
a highly doped upper region of a second conductivity type formed between the highly doped regions; and
device isolation layers formed between each highly doped region and a corresponding highly doped upper region.
8. The integrated semiconductor device of claim 7 , wherein the sensing region directly contacts one of the deep trenches.
9. The integrated semiconductor device of claim 1 , wherein the second transistor comprises a Laterally Diffused Metal-Oxide Semiconductor (LDMOS) transistor or a non-volatile memory device.
10. The integrated semiconductor device of claim 9 , wherein the LDMOS transistor comprises:
a first drift region of a first conductivity type formed on the substrate;
a body region of a second conductivity type;
a source region formed in the body region; and
a first drain region formed in the first drift region.
11. The integrated semiconductor device of claim 1 ,
wherein each of the deep trenches comprises a deep trench portion and a shallow trench portion formed overlapping with the deep trench portion.
12. An integrated semiconductor device, comprising:
a transistor formed on a semiconductor substrate;
an isolation structure surrounding the transistor, wherein the isolation structure comprises trenches comprising a first trench and a second trench formed apart from each other;
a first trapping region of a first conductivity type formed between the first and second trenches;
a second trapping region of a second conductivity type formed on a part of the first trench;
a third trapping region of the second conductivity type formed on a part of the second trench; and
a trench bottom doping region of the second conductivity type formed on an end of the trenches.
13. The integrated semiconductor device of claim 12 , wherein the first trapping region comprises:
a buried layer;
a well region formed on the buried layer; and
a highly doped region formed on the well region.
14. The integrated semiconductor device of claim 12 , wherein the second and third trapping regions respectively comprise a well region, and a highly doped region formed on the well region.
15. The integrated semiconductor device of claim 12 , wherein the transistor comprises:
a Hall sensor, wherein the Hall sensor comprises
a sensing region formed on the substrate,
highly doped regions of the first conductivity type formed on the sensing region and located apart from each other,
a highly doped upper region of the second conductivity type formed between the highly doped regions, and
isolation layers formed between one of the highly doped regions and the highly doped upper region.