IP Library Granted Patent US 10,217,706
Granted Patent B2
US 10,217,706 · App. 15/685,907 · Granted Feb 26, 2019

Semiconductor constructions

Inventors: Vishal Sipani (Boise, ID); Kyle Armstrong (Meridian, ID); Michael D. Hyatt (Boise, ID); Michael Dean Van Patten (Fruitland, ID); David A. Kewley (Boise, ID); Ming-Chuan Yang (Meridian, ID)
Assignee: Micron Technology, Inc.
H01L23/525H01L21/0337H01L21/0338H01L21/31144H01L21/32139H01L21/76816H01L23/528H01L23/5329H01L23/53209H01L23/53257H01L23/53271H01L2924/0002
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Quick Facts
Patent No.
US 10,217,706
App. No.
15/685,907
Granted
Feb 26, 2019
Kind
B2
Abstract

Some embodiments include methods of forming electrically conductive lines. Photoresist features are formed over a substrate, with at least one of the photoresist features having a narrowed region. The photoresist features are trimmed, which punches through the narrowed region to form a gap. Spacers are formed along sidewalls of the photoresist features. Two of the spacers merge within the gap. The photoresist features are removed to leave a pattern comprising the spacers. The pattern is extended into the substrate to form a plurality of recesses within the substrate. Electrically conductive material is formed within the recesses to create the electrically conductive lines. Some embodiments include semiconductor constructions having a plurality of lines over a semiconductor substrate. Two of the lines are adjacent to one another and are substantially parallel to one another except in a region wherein said two of the lines merge into one another.

Claims (15)

1. A semiconductor construction comprising a pair of adjacent electrically conductive lines, the pair of adjacent lines being substantially parallel to one another except in a region where the lines merge into one another; the pair of lines curving inward toward one another in the region where the lines merge, each of the lines being collinear on either side of the region where the lines merge.

2. The construction of claim 1 , wherein the electrically conductive lines are spaced from one another by electrically insulative material.

3. The construction of claim 1 , wherein the electrically conductive lines have a pitch of from 10 nm to 100 nm.

4. The construction of claim 3 , wherein the electrically conductive lines have a maximum width of less than or equal to about one-fourth the pitch.

5. A semiconductor construction comprising a plurality of lines over a semiconductor substrate; two of the lines being adjacent to one another being a first line and a second line and being substantially parallel to one another along a first direction except in a region wherein said two of the lines merge into one another, the two lines curving inward toward one another in the region where the lines merge; the merge region comprising a connection portion that extends between the first line and the second line in a second direction, the connection portion having a width along the first direction that is less that a width across each of the lines in the second direction, the lines comprising a dielectric material.

6. The construction of claim 5 , wherein the dielectric material comprises silicon nitride.

7. The construction of claim 5 , wherein the dielectric material comprises silicon oxide.

8. The construction of claim 5 , wherein the lines are spaced from one another by an electrically conductive material in regions where the lines are parallel to one another.

9. The construction of claim 8 , wherein the electrically conductive material comprises metal.

10. The construction of claim 8 , wherein the electrically conductive material comprises metal carbide.

11. The construction of claim 8 , wherein the electrically conductive material comprises metal silicide.

12. The construction of claim 8 , wherein the electrically conductive material comprises conductively-doped semiconductor material.

13. A semiconductor construction comprising a plurality of lines over a semiconductor substrate; the lines being on a pitch within a range of from about 10 nanometers to about 100 nanometers; two of the lines being adjacent to one another; one of said two of the lines being a first line and the other being a second line; the first and second lines having first and second segments, respectively; the first and second segments being substantially parallel to one another along a first direction; the first and second lines merging with one another in a region; the region where the first and second lines merge having a line connection extending between the two lines, the line connection being narrower along the first direction than a width of the lines along the first and second segments of the lines, the two lines curving inward toward one another in the region where the lines merge; the first and second lines comprising dielectric material, and being spaced from one another along the substantially parallel first and second segments by electrically conductive material.

14. The construction of claim 13 , wherein the electrically conductive material has sidewall surfaces that directly contacts the dielectric material.

15. The construction of claim 13 , wherein each of the two lines are co-linear along the line outside the region where the first and second lines merge.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050709/0838 →
RELEASE OF SECURITY INTEREST Recorded Jul 20, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046597/0333 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 6 TO PATENT SECURITY AGREEMENT Recorded Nov 1, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 044348/0253 →
SUPPLEMENT NO. 6 TO PATENT SECURITY AGREEMENT Recorded Nov 1, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 044653/0333 →
Continuity (3)
Continuation 14699664 · Apr 29, 2015
Division 13660860 · Oct 25, 2012
Related Publication 20170352616A1 · Dec 7, 2017