Apparatus and methods to perform read-while write (RWW) operations
A plurality of block configurations may be employed for read while write operations. In one apparatus example, a plurality of block configurations may be employed. Block configurations may include an arrangement of similarly doped semiconductor switches. Block configurations may select a respective tile of a memory array, a particular memory cell of the respective tile, and select a memory operation to apply to the particular memory cell. Immediately adjacent block configurations within a particular slice of the memory array may be substantially mirrored and immediately adjacent block configurations in separate immediately adjacent slices of the memory array may be substantially similar. Similarly doped diffusion regions for similarly doped semiconductor switches in substantially mirrored block configurations may be arranged to electrically share a common potential signal value level. Other apparatus and methods are also disclosed.
1. A memory device, comprising:
a memory array that comprises two or more block configurations, each of the two or more block configurations comprising an arrangement of transistors comprising a first group of transistors configured to receive a memory operation and a second group of transistors configured to select a slice of the memory array representing a respective combination of row lines and column lines of the memory array, wherein at least two of the block configurations are mirrored; and
a memory controller in electronic communication with the row lines and the column lines, wherein the slice of the memory array comprises a first signal path associated with a read operation and a second signal path associated with a write operation, wherein at least two transistors of the first group of transistors electrically connects a selected slice of the memory array to both the first signal path and the second signal path, wherein the first group of transistors is positioned on a same side of the selected slice of the memory array and transistors of the second group of transistors are positioned on opposing sides of the selected slice of the memory array, [[and]] wherein each transistor of the first group of transistors is coupled to each transistor of the second group of transistors, and wherein the transistors in the mirrored block configurations comprise p-type field-effect transistors, the p-type field-effect transistors providing a smaller semiconductor area in a block configuration relative to n-type field-effect transistors.
2. The memory device of claim 1 , wherein each of the two or more block configurations comprises a memory slice decoder a memory operation decoder.
3. The memory device of claim 1 , wherein identically doped diffusion regions of transistors in the mirrored block configurations electronically share a common potential signal level.
4. The memory device of claim 1 , wherein a subset of the transistors in the two or more block configurations have similarly doped n-well diffusion regions and are arranged to electronically share a common potential signal level.
5. The memory device of claim 1 , further comprising:
a voltage source configured to apply a negative voltage to a gate of a p-type field-effect transistor from at least one of the one or more memory operation decoders during a read operation.
6. The memory device of claim 1 , further comprising:
a first voltage source configured to apply a ground signal to a gate of a p-type field-effect transistor from at least one of the one or more memory operation decoders during a write operation.
7. The memory device of claim 6 , further comprising:
a second voltage source configured to apply a source voltage to n-wells of one or more deselected transistors from at least one of the one or more memory operation decoders during a write operation.
8. The memory device of claim 1 , further comprising:
a decoder to provide a signal to at least one of the two or more block configurations, the at least one of the two or more block configurations is configured to select a particular partition of the memory array based at least in part on the signal.
9. The memory device of claim 1 , wherein at least one of the two or more block configurations is configured to perform a read-while-write operation.
10. A memory device comprising:
a memory controller in electronic communication with one or more memory cells, the memory controller operable to:
select a memory cell;
apply a first voltage to a first signal path associated with a read operation, and
apply a second voltage to a second signal path associated with a write operation;
a memory array comprising one or more memory cells and two or more block configurations, each of the two or more block configurations comprising:
a first transistor configured to receive a first signal from the memory controller to select a first memory cell of the one or more memory cells, the first transistor coupled with at least one of the one or more memory cells and the first signal path;
a second transistor configured to receive a second signal from the memory controller to select a second memory cell of the one or more memory cells, the second transistor coupled with at least one of the one or more memory cells and the second signal path;
a third transistor configured to receive a third signal from the memory controller to receive the read operation, the third transistor coupled with the first memory cell or the second memory cell and the first signal path; and
a fourth transistor configured to receive a fourth signal from the memory controller to receive the write operation, the fourth transistor coupled with the first memory cell or the second memory cell and the second signal path,
wherein the third transistor and the fourth transistor electrically connect at least one of the first or second selected memory cell to both the first signal path and the second signal path,
wherein the first transistor and the second transistor are positioned on opposing sides of the selected memory cell at a time period when the first memory cell or the second memory cell is selected,
wherein the third transistor and the fourth transistor are positioned on a same side of the selected memory cell at the time period when the first memory cell or the second memory cell is selected,
wherein the first transistor and the second transistor are each coupled to the third transistor and the fourth transistor, and
wherein the first transistor, the second transistor, the third transistor, and the fourth transistor of the two or more block configurations comprise p-type field-effect transistors, the p-type field-effect transistors providing a smaller semiconductor area in a block configuration relative to n-type field-effect transistors.
11. The memory device of claim 1 , wherein the transistors are identically doped.
12. The memory device of claim 10 , wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are identically doped.
13. The memory device of claim 1 , wherein the first signal path is employed in a read operation associated with a first memory partition and the second signal path is employed in a write operation associated with a second memory partition at a same time period.
14. The memory device of claim 10 , wherein the first signal path is employed in a read operation associated with a first memory partition and the second signal path is employed in a write operation associated with a second memory partition at a same time period.