Refresh in non-volatile memory
View Patent ↗The present disclosure includes apparatuses and methods related to refresh in memory. An example apparatus can refresh a memory cell of an array of memory cells in response to the array of memory cells being accessed a threshold number of accesses.
1. An apparatus, comprising:
an array of memory cells;
a counter configured to:
determine an access count of the array of memory cells; and
a controller configured to:
refresh a memory cell of the array of memory cells in response to the access count of the array of memory cells being a threshold number.
2. The apparatus of claim 1 , wherein the controller is configured to determine a refresh rate based on the threshold number.
3. The apparatus of claim 1 , wherein the controller is configured to determine refresh rate based on a threshold miss rate.
4. The apparatus of claim 2 , wherein the controller is configured to determine the refresh rate based on a static workload.
5. The apparatus of claim 2 , wherein the controller is configured to determine the refresh rate periodically based on a dynamic workload.
6. The apparatus of claim 2 , wherein the controller is configured to identify a type of workload based on locations of accesses and an access rate.
7. The apparatus of claim 2 , wherein the controller is configured to determine the refresh rate periodically based on dynamic data.
8. The apparatus of claim 2 , wherein the controller is configured to determine the refresh rate periodically based on a type of workload.
9. An apparatus, comprising:
an array of memory cells;
a counter configured to:
determine an access count of the array of memory cells; and
a controller configured to:
determine a refresh rate of the array of memory cells; and
refresh a memory cell of the array of memory cells in response to the access count of the array of memory cells being a threshold number, wherein the threshold number is based on the refresh rate.
10. The apparatus of claim 9 , wherein the controller is configured to refresh the memory cell of the array of memory cells that was last accessed.
11. The apparatus of claim 9 , wherein the controller is configured to refresh a randomly selected memory cell of the array of memory cells.
12. The apparatus of claim 9 , wherein the controller is configured to refresh a memory cell with an access count that is above the threshold number.
13. The apparatus of claim 9 , wherein the counter is included in a self-monitoring, analysis and reporting technology (SMART) system used to control host and background accesses.
14. An apparatus, comprising:
an array of memory cells;
a counter configured to:
determine an access count of the array of memory cells; and
a controller configured to:
determine a refresh rate of the array of memory cells; and
refresh a memory cell of the array of memory cells that was last accessed in response to the access count of the array of memory cells being a threshold number, wherein the threshold number is based on the refresh rate and the refresh rate is based on a miss rate of the array of memory cells.
15. The apparatus of claim 14 , wherein the controller is configured to determine the refresh rate based on a threshold miss rate.
16. The apparatus of claim 14 , wherein the controller is configured to determine the miss rate based on a number of memory cells that fail to refresh within the threshold number.
17. The apparatus of claim 14 , wherein the controller is configured to reduce the miss rate by increasing the refresh rate.
18. The apparatus of claim 14 , wherein the controller is configured to determine the refresh rate to reduce write amplification.
19. The apparatus of claim 14 , wherein the controller is configured to determine the refresh rate that increases the threshold number based on a threshold miss rate.
20. The apparatus of claim 14 , wherein the controller is configured to determine the refresh rate that makes the threshold number 500 accesses or more based on a threshold miss rate.
21. The apparatus of claim 14 , wherein the controller is configured to refresh the memory cell of the array of memory cells that was last accessed to protect the array of memory cells from attacks that continuously access a memory cell or a number of memory cells.
22. The apparatus of claim 14 , wherein the controller is configured to refresh the memory cell of the array of memory cells that was last accessed to protect the array of memory cells from heavy access loads that continuously access a memory cell or a number of memory cells.
23. A method, comprising:
accessing a memory cell of an array of memory cells; and
refreshing the memory cell of the array of memory cells in response to an access count of the array of memory cells being a threshold number.
24. The method of claim 23 , further comprising determining a refresh rate based on the threshold number.
25. The method of claim 23 , further comprising determining a refresh rate based on a threshold miss rate.
26. The method of claim 25 , further comprising determining the refresh rate based on a static workload by access locations and rate of accesses.
27. The method of claim 25 , further comprising determining the refresh rate based on a dynamic workload by access locations and access rate.
28. A method, comprising:
determining a refresh rate of an array of memory cells;
accessing a memory cell of the array of memory cells; and
refreshing the memory cell of the array of memory cells in response to an access count of the array of memory cells being a threshold number, wherein the threshold number is based on the refresh rate and the refresh rate is based on a miss rate of the array of memory cells.
29. The method of claim 28 , wherein the threshold number includes background accesses and host accesses.
30. The method of claim 28 , further comprising determining the refresh rate based on a number of memory cells that fail to refresh within the threshold number.
31. The method of claim 28 , further comprising increasing the threshold number to decrease the miss rate.
32. The method of claim 28 , further comprising determining the refresh rate to decrease write amplification.
33. The method of claim 28 , further comprising refreshing the memory cell of the array to protect the array of memory cells from attacks that continuously access a memory cell or a number of memory cells.
34. The method of claim 28 , further comprising refreshing the memory cell of the array of memory cells to protect the array of memory cells from heavy access loads that continuously access a memory cell or a number of memory cells.