IP Library Granted Patent US 10,339,005
Granted Patent B2
US 10,339,005 · App. 15/689,114 · Granted Jul 2, 2019

Stripe mapping in memory

Inventors: Edward McGlaughlin (Minneapolis, MN); Joseph M. Jeddeloh (Shoreview, MN)
Assignee: Micron Technology, Inc.
G06F11/108G06F3/0614G06F3/0629G06F3/0689G06F11/10G06F11/1012
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Quick Facts
Patent No.
US 10,339,005
App. No.
15/689,114
Granted
Jul 2, 2019
Kind
B2
Abstract

Examples of the present disclosure provide apparatuses and methods related to redundant array of independent disks (RAID) stripe mapping in memory. An example method comprises writing data in a number of stripes across a storage volume of a plurality of memory devices according to a stripe map; wherein each of the number of stripes includes a number of elements; and wherein the stripe map includes a number of stripe indexes to identify the number of stripes and a number of element identifiers to identify elements included in each of the number of stripes.

Claims (29)

1. A method for stripe mapping, comprising:

storing a first stripe map, wherein the first stripe map includes a number of stripe indexes to identify a number of stripes stored in a plurality of memory devices and a number of element identifiers to identify elements included in each of the number of stripes;

storing a second stripe map, wherein the second stripe map is an inverse stripe map of the first stripe map; and

performing a redundant array of independent disks (RAID) read error recovery operation using the second stripe map to identify a plurality of stripes that each include a bad element, wherein the RAID read error recovery operation corrects data in the bad element using parity data, moves the corrected data to a different element, and updates element identifiers of the plurality of stripes to include an identifier for the different element.

2. The method of claim 1 , wherein the method includes creating the first stripe map by associating each of the number of stripe indexes with a portion of the elements included in each of the number of stripes.

3. The method of claim 1 , wherein the method includes creating the first stripe map by associating each of the number of stripes with a parity element identifier.

4. The method of claim 1 , wherein the method includes creating the first stripe map by selecting the elements to include in the number of stripes based on a bit error rate associated with the elements.

5. The method of claim 1 , wherein the method includes creating the first stripe map by selecting the pages to include in the number of stripes based on a location of the pages within the plurality of memory devices.

6. The method of claim 1 , further including writing data in the number of stripes includes splitting the data into the number of elements and writing the number of elements to the plurality of memory devices.

7. The method of claim 6 , further including writing the number of elements to the plurality of memory devices includes writing at least one element to each of the plurality of memory devices.

8. An apparatus, comprising:

a number of memory devices; and

a controller coupled to the number of memory devices and configured to:

store a first stripe map comprising element identifiers for each element of a number of stripes in the number of memory devices;

write data to the number of memory devices, wherein the data is written to elements of the number of stripes as defined by the first stripe map;

store a second stripe map comprising an inverse stripe map of the first stripe map; and

perform a read error recovery operation using the second stripe map to identify a plurality of stripes that each include a bad element, wherein the read error recovery operation corrects data from the bad element in each of the plurality of stripes using parity data, moves the corrected data to a different element, and updates element identifiers for the plurality of stripes to include an identifier for the different element.

9. The apparatus of claim 8 , wherein the element identifiers for each element includes channel, device, block, and page information.

10. The apparatus of claim 8 , wherein elements of a particular stripe include varied bit error rates.

11. The apparatus of claim 8 , wherein elements of a particular stripe are selected based on physical locations in the number of memory devices.

12. The apparatus of claim 8 , wherein the controller is configured to update the first stripe map based on the read error recovery operation.

13. A method for stripe mapping, comprising:

storing a first stripe map, wherein the first stripe map is indexed by stripe and identifies each element that is associated with each particular stripe of a number of stripes in a plurality of memory devices;

storing a second stripe map, the second stripe map is indexed by element and identifies each stripe that is associated with each particular element of a number of elements in a plurality of memory devices; and

performing a read error recovery operation using the second stripe map to identify a plurality of stripes that each include a number of bad elements, wherein the read error recovery operation corrects data from the number of bad elements in each of the plurality of stripes using parity data, moves the corrected data to a different number of elements, and updates element identifiers for the plurality of stripes to include identifiers for the different number of elements.

14. The method of claim 13 , wherein the method includes performing the read error recovery operation in response to an error correction code (ECC) operation failure.

15. The method of claim 13 , wherein creating the first stripe map includes identifying each of the particular elements with a page identifier.

16. The method of claim 13 , wherein the method includes updating the first stripe map by removing element identifiers of bad elements from the first stripe map.

17. The method claim 13 , wherein the first stripe map includes a parity element identifier in each of the number of stripes.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050709/0838 →
RELEASE OF SECURITY INTEREST Recorded Jul 20, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046597/0333 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 6 TO PATENT SECURITY AGREEMENT Recorded Nov 1, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 044653/0333 →
SUPPLEMENT NO. 6 TO PATENT SECURITY AGREEMENT Recorded Nov 1, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 044348/0253 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 29, 2017
From: MCGLAUGHLIN, EDWARD; JEDDELOH, JOSEPH M.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 043432/0629 →
Continuity (2)
Continuation 14735838 · Jun 10, 2015
Related Publication 20170357467A1 · Dec 14, 2017
Cited By (4)
US 12,298,902 US 12,360,892 US 12,504,899 US 12,572,468