IP Library Granted Patent US 10,068,655
Granted Patent B2
US 10,068,655 · App. 15/689,955 · Granted Sep 4, 2018

Inferring threshold voltage distributions associated with memory cells via interpolation

Inventors: Zhenlei Shen (Boise, ID); William H. Radke (Los Gatos, CA)
Assignee: Micron Technology, Inc.
G11C16/34G11C11/5621G11C11/5628G11C11/5642G11C16/0483G11C16/10G11C16/3404G11C16/3418
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Quick Facts
Patent No.
US 10,068,655
App. No.
15/689,955
Granted
Sep 4, 2018
Kind
B2
Abstract

Apparatuses and methods for inferring threshold voltage distributions associated with memory cells via interpolation are described herein. A number of embodiments include determining soft data for a group of memory cells each programmed to one of a number of data states, wherein the soft data comprises a number of different soft data values, determining a quantity of memory cells associated with each of the different soft data values, and inferring at least a portion of a threshold voltage distribution associated with the group of memory cells via an interpolation process using the determined quantities of memory cells associated with each of the different soft data values.

Claims (48)

1. An apparatus, comprising:

an array of memory cells; and

a controller coupled to the array and configured to:

determine a quantity of memory cells associated with each of a number of different soft data values; and

infer at least a portion of a threshold voltage distribution associated with the memory cells using the determined quantities.

2. The apparatus of claim 1 , wherein the controller is configured to:

assign a threshold voltage value to represent each voltage spacing between a number of sensing voltages for the memory cells; and

infer the at least a portion of the threshold voltage distribution using the assigned threshold voltage values.

3. The apparatus of claim 2 , wherein each voltage spacing between the number of sensing voltages is a same voltage amount.

4. The apparatus of claim 2 , wherein each voltage spacing between the number of sensing voltages is a different voltage amount.

5. The apparatus of claim 2 , wherein:

the number of sensing voltages for the memory cells includes at least five sensing voltages;

at least two of the voltage spacings are a same voltage amount; and

at least two of the voltage spacings are different voltage amounts.

6. The apparatus of claim 1 , wherein the number of different soft data values includes at least four different soft data values.

7. A method for operating memory, comprising:

determining soft data for a group of memory cells, wherein the soft data comprises a number of different soft data values;

determining a quantity of memory cells associated with each of the different soft data values; and

inferring at least a portion of a threshold voltage distribution associated with the group of memory cells using the determined quantities.

8. The method of claim 7 , wherein each respective memory cell of the group of memory cells is programmed to one of a number of data states.

9. The method of claim 7 , wherein the method includes:

normalizing the determined quantities; and

inferring the at least a portion of the threshold voltage distribution using the normalized quantities.

10. The method of claim 7 , wherein the method includes:

determining the soft data using a number of sensing voltages; and

assigning a threshold voltage value to represent each voltage spacing between the number of sensing voltages.

11. The method of claim 10 , wherein the method includes inferring the at least a portion of the threshold voltage distribution using the assigned threshold voltage values.

12. The method of claim 10 , wherein assigning the threshold voltage value to represent each voltage spacing includes mapping the voltage spacings based on a previous threshold voltage distribution associated with the group of memory cells.

13. The method of claim 12 , wherein the mapping of the voltage spacings is a base mapping.

14. The method of claim 12 , wherein the mapping of the voltage spacings is a heuristic mapping.

15. The method of claim 7 , wherein the method includes:

using a controller to determine the soft data for the group of memory cells;

using the controller to determine the quantity of memory cells associated with each of the different soft data values; and

using the controller to infer the at least a portion of the threshold voltage distribution.

16. An apparatus, comprising:

an array of memory cells; and

a controller coupled to the array and configured to:

determine a quantity of memory cells associated with each of a number of different soft data values;

normalize the determined quantities; and

infer at least a portion of a threshold voltage distribution associated with the memory cells using the normalized quantities.

17. The apparatus of claim 16 , wherein the controller is configured to normalize the determined quantities by equalizing a weight of each determined quantity.

18. The apparatus of claim 16 , wherein the controller is configured to:

determine the quantity of memory cells associated with each of the number of different soft data values by creating a histogram for each of the number of different soft data values; and

normalize the determined quantities by adjusting a height of each histogram.

19. The apparatus of claim 18 , wherein:

the height of each histogram before the adjustment corresponds to the quantity of memory cells associated with the soft data value for that histogram; and

the height of each histogram after the adjustment corresponds to the normalized quantity of memory cells associated with the soft data for that histogram.

20. The apparatus of claim 18 , wherein the controller includes a histogram builder configured to create the histogram for each of the number of different soft data values.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050709/0838 →
RELEASE OF SECURITY INTEREST Recorded Jul 20, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046597/0333 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 6 TO PATENT SECURITY AGREEMENT Recorded Nov 1, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 044348/0253 →
SUPPLEMENT NO. 6 TO PATENT SECURITY AGREEMENT Recorded Nov 1, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 044653/0333 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 29, 2017
From: SHEN, ZHENLEI; RADKE, WILLIAM H.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 043439/0791 →
Continuity (4)
Continuation 15091078 · Apr 5, 2016
Continuation 14474500 · Sep 2, 2014
Continuation 13600563 · Aug 31, 2012
Related Publication 20170358366A1 · Dec 14, 2017