IP Library Granted Patent US 10,453,802
Granted Patent B2
US 10,453,802 · App. 15/691,455 · Granted Oct 22, 2019

Semiconductor package structure, semiconductor device and method for manufacturing the same

Inventor: Ian Hu (Kaohsiung, TW)
Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
H01L23/552H01L21/4871H01L21/56H01L23/13H01L23/3192H01L23/36H01L23/49838H01L23/49866H01L23/5383H01L23/5384H01L23/5385H01L25/0652H01L2224/16225H01L2224/73253H01L2224/94H01L2224/97H01L2225/06517H01L2225/06537H01L2225/06572H01L2225/06589H01L2924/15192H01L2924/15311H01L2924/15313H01L2924/19105H01L2924/3025
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Quick Facts
Patent No.
US 10,453,802
App. No.
15/691,455
Granted
Oct 22, 2019
Kind
B2
Abstract

A semiconductor package structure includes a substrate, at least one first semiconductor element, a heat dissipation structure and an insulation layer. The at least one first semiconductor element is attached to the substrate, and has a first surface and a second surface opposite to the first surface. The first surface of the at least one first semiconductor element faces the substrate. The heat dissipation structure is disposed on the second surface of the at least one first semiconductor element. The insulation layer is disposed on the heat dissipation structure, and defines a plurality of openings extending through the insulation layer and exposing a plurality of exposed portions of the heat dissipation structure.

Claims (42)

1. A semiconductor package structure, comprising:

a substrate;

at least one first semiconductor element attached to the substrate, and having a first surface, a second surface opposite to the first surface, and a side surface extending between the first surface and the second surface, wherein the first surface of the at least one first semiconductor element faces the substrate;

a heat dissipation structure disposed on the second surface of the first semiconductor element;

an insulation layer having a bottom surface, the insulation layer disposed on the heat dissipation structure, and defining a plurality of openings extending through the insulation layer and exposing a plurality of exposed portions of the heat dissipation structure; and

a first encapsulant covering the side surface of the at least one first semiconductor element and having a bottom surface substantially coplanar with the bottom surface of the insulation layer.

2. The semiconductor package structure according to claim 1 , wherein a length of the heat dissipation structure is substantially equal to a length of the second surface of the at least one first semiconductor element.

3. The semiconductor package structure according to claim 1 , wherein a side surface of the heat dissipation structure is substantially coplanar with the side surface of the at least one first semiconductor element.

4. The semiconductor package structure according to claim 1 , wherein the heat dissipation structure includes a first metal layer.

5. The semiconductor package structure according to claim 4 , wherein the first metal layer includes copper.

6. The semiconductor package structure according to claim 4 , wherein the heat dissipation structure further includes a second metal layer, and the first metal layer is disposed between the second metal layer and the second surface of the at least one first semiconductor element.

7. The semiconductor package structure according to claim 6 , wherein the second metal layer includes nickel, gold, a gold-nickel alloy, a nickel-vanadium alloy, palladium or molybdenum.

8. The semiconductor package structure according to claim 1 , wherein the insulation layer includes a polyimide, polybenzobisoxazole, a polyamide, a dielectric material, a solder resist or a combination thereof.

9. The semiconductor package structure according to claim 1 , wherein a width of at least one of the openings of the insulation layer is in a range of about 0.1 millimeters (mm) to about 3 mm.

10. The semiconductor package structure according to claim 1 , wherein a gap between two openings of the insulation layer is in a range of about 0.1 mm to about 0.5 mm.

11. The semiconductor package structure according to claim 1 , wherein the substrate has a first surface and a second surface opposite to the first surface, the first surface of the at least one first semiconductor element faces the second surface of the substrate, and the semiconductor package structure further comprises:

at least one second semiconductor element attached to the first surface of the substrate; and

a second encapsulant disposed on the first surface of the substrate covering the second semiconductor element.

12. The semiconductor package structure according to claim 11 , further comprising a shielding layer disposed on a side surface of the second encapsulant and a side surface of the substrate.

13. A semiconductor device, comprising:

a semiconductor package structure comprising:

a substrate;

at least one first semiconductor element attached to the substrate, and having a first surface, a second surface opposite to the first surface, and a side surface extending between the first surface and the second surface, wherein the first surface of the at least one first semiconductor element faces the substrate;

a heat dissipation structure disposed on the second surface of the at least one first semiconductor element;

an insulation layer having a bottom surface, the insulation layer disposed on the heat dissipation structure, and defining a plurality of openings extending through the insulation layer and exposing a plurality of portions of the heat dissipation structure; and

an encapsulant covering the side surface of the at least one first semiconductor element and having a bottom surface substantially coplanar with the bottom surface of the insulation layer;

a circuit board disposed apart from the semiconductor package structure; and

a plurality of first conductive elements connecting the exposed portions of the heat dissipation structure to the circuit board.

14. The semiconductor device according to claim 13 , wherein the semiconductor package structure further comprises at least one internal connector electrically connected to the substrate, and the semiconductor device further comprises a plurality of second conductive elements electrically connecting the at least one internal connector to the circuit board.

15. The semiconductor device according to claim 14 , wherein one or more of the second conductive elements is a solder ball or a solder post.

16. The semiconductor device according to claim 13 , wherein one or more of the first conductive elements is a solder ball or a solder post.

17. A method for manufacturing a semiconductor package structure, comprising:

providing at least one first semiconductor element having a first surface, a second surface opposite to the first surface, and a side surface extending between the first surface and the second surface;

forming a heat dissipation structure on the second surface of the at least one first semiconductor element;

forming an insulation layer on the heat dissipation structure, wherein the insulation layer has a bottom surface and defines a plurality of openings extending through the insulation layer and exposing a plurality of portions of the heat dissipation structure;

mounting the at least one first semiconductor element to a substrate; and

forming a first encapsulant to cover the side surface of the at least one first semiconductor element, wherein the first encapsulant has a bottom surface substantially coplanar with the bottom surface of the insulation layer.

18. The method according to claim 17 , wherein mounting the first semiconductor element to the substrate comprises mounting the at least one first semiconductor element to a first surface of the substrate, and the method further comprises:

mounting at least one second semiconductor element to a second surface of the substrate; and

forming a second encapsulant to cover the at least one second semiconductor element.

19. The method according to claim 18 , further comprising:

forming a shielding layer on a side surface of the second encapsulant, a side surface of the substrate and a side surface of the first encapsulant.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 30, 2017
From: HU, IAN
To: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
Reel/Frame 043452/0871 →
Continuity (1)
Related Publication 20190067207A1 · Feb 28, 2019
Cited By (2)
US 12,308,329 US 12,564,111