Apparatuses and/or methods for operating a memory cell as an anti-fuse
Embodiments disclosed herein relate to operating a memory cell as an anti-fuse, such as for use in phase change memory, for example.
1. A memory device, comprising:
a memory cell having a reprogrammable resistance range, the memory cell comprising a chalcogenide material and a metal plug; and
a selector configured to set the memory cell to a one-time programmable resistance level for the memory cell outside the reprogrammable resistance range.
2. The memory device of claim 1 , wherein the selector is configured to set the memory cell to the one-time programmable resistance level outside the reprogrammable resistance range by forming a resistance path at least partially surrounded by the chalcogenide material.
3. The memory device of claim 2 , wherein the resistance path is a metallic path.
4. The memory device of claim 3 , wherein the selector is configured to form the metallic path at least in part by causing metallic ions to migrate from the metal plug into the chalcogenide material.
5. The memory device of claim 3 , wherein the memory cell is configured to operate as an anti-fuse based at least in part on the metallic path.
6. The memory device of claim 2 , wherein the resistance path is a void.
7. The memory device of claim 6 , wherein the selector is configured to form the void at least in part by applying a bias current to the memory cell.
8. The memory device of claim 6 , wherein the memory cell is configured to operate as a fuse based at least in part on the void.
9. The memory device of claim 1 , wherein the selector is configured to set the memory cell to the one-time programmable resistance level outside the reprogrammable resistance range by applying a directional bias current to the memory cell.
10. The memory device of claim 9 wherein the directional bias current is a forward bias current sufficient to operate the memory cell as an anti-fuse.
11. The memory device of claim 9 wherein the directional bias current is a negative bias current sufficient to operate the memory cell as a fuse.
12. A method comprising:
applying a directional bias current to a memory cell comprising a chalcogenide material and a metal plug,
wherein the memory cell has a reprogrammable resistance range and the directional bias current has a magnitude to form a resistance path at least partially surrounded by the chalcogenide material, and
wherein the memory cell has a read-only resistance outside the reprogrammable resistance range after the resistance path is formed.
13. The method of claim 12 , Therein forming the resistance path comprises operating the memory cell as an anti-fuse.
14. The method of claim 12 , wherein forming the resistance path comprises operating the memory cell as a fuse.
15. The method of claim 12 , wherein forming the resistance path comprises forming a metallic path.
16. The method of claim 15 , wherein forming the metallic path comprises causing migration of metallic ions from the metal plug.
17. The method of claim 12 , wherein forming the resistance path comprises forming a void.
18. The method of claim 12 , further comprising:
incorporating the memory cell into an integrated circuit after forming the resistance path.
19. A memory device, comprising:
a memory array including a plurality of memory cells, each memory cell in the memory array having a reprogrammable resistance range and comprising a chalcogenide material and a metal plug;
a first selector configured to set a first memory cell to a first resistance level, the first resistance level being a one-time programmable resistance level for the memory cell that is outside the reprogrammable resistance range; and
a second selector configured to set a second memory cell to a second resistance level, the second resistance level within the reprogrammable resistance range.
20. The memory device of claim 19 , wherein the first selector is configured to set the first memory cell to the first resistance level by forming a resistance path at least partially surrounded by the chalcogenide material.
21. The memory device of claim 19 , wherein the second selector is configured to set the second memory cell to the second resistance level by switching the chalcogenide material between at least two resistance states within the reprogrammable resistance range.