IP Library Granted Patent US 10,217,866
Granted Patent B2
US 10,217,866 · App. 15/696,201 · Granted Feb 26, 2019

Semiconductor device and method of forming the same

Inventors: Chi-Hsuan Cheng (Kaohsiung, TW); Cheng-Pu Chiu (New Taipei, TW); Yu-Chih Su (Tainan, TW); Chih-Yi Wang (Tainan, TW); Chin-Yang Hsieh (Tainan, TW); Tien-Shan Hsu (Tainan, TW); Yao-Jhan Wang (Tainan, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L29/7846H01L21/823821H01L21/823878H01L27/0924H01L29/0653
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Quick Facts
Patent No.
US 10,217,866
App. No.
15/696,201
Granted
Feb 26, 2019
Kind
B2
Abstract

A semiconductor device and a method of forming the same, the semiconductor device includes a first and a second fin structures, a first, a second and a third isolation structures, and a first and a second gate structures. The first and second fin structures are disposed in a substrate. The first isolation structure is disposed in the substrate and surrounds the first and second fin structures. The second isolation structure is disposed in the first fin structure, and a top surface of the second isolation structure is leveled with a top surface of the first and second fin structures. The third isolation structure is disposed in the second fin shaped structure, and a top surface of the third isolation structure is lower than the top surface of the first and second fin structures. The first and second gate structures are disposed on the second and third isolation structures, respectively.

Claims (19)

1. A semiconductor device, comprising:

a first fin shaped structure and a second fin shaped structure disposed on a substrate;

a first isolation structure disposed on the substrate, surrounded the first fin shaped structure and the second fin shaped structure;

a second isolation structure disposed in the first fin shaped structure;

a third isolation structure disposed in the second fin shaped structure, wherein a top surface of the third isolation structure and a top surface of the second isolation structure are in different heights, and the top surface of the third isolation structure is lower than a top surface of the second fin shaped structure; and

a first gate and a second gate, disposed on the second isolation structure and the third isolation structure, respectively; and

a fourth isolation structure disposed between the first fin shaped structure and the second fin shaped structure.

2. The semiconductor device according to claim 1 , wherein the second isolation structure and the third isolation structure comprises different dielectric materials.

3. The semiconductor device according to claim 1 , wherein the third isolation structure comprises a bilayer structure.

4. The semiconductor device according to claim 3 , wherein the bilayer structure comprises an oxide layer and a nitride layer.

5. The semiconductor device according to claim 1 , wherein the second isolation structure comprises a monolayer structure.

6. The semiconductor device according to claim 5 , wherein the monolayer structure only comprises oxide.

7. The semiconductor device according to claim 1 , further comprising:

a first doped region, disposed in the first fin shaped structure and having a first conductive type; and

a second doped region, disposed in the second fin shaped structure and having a second conductive type being complementary to the first conductive type.

8. The semiconductor device according to claim 7 , wherein the first conductive type is p-type, and the second conductive type is n-type.

9. The semiconductor device according to claim 7 , wherein the first doped region is disposed at two sides of the first gate in the first fin shaped structure.

10. The semiconductor device according to claim 7 , wherein the second doped region is disposed at two sides of the second gate in the second fin shaped structure.

11. The semiconductor device according to claim 1 , wherein a portion of the second gate is disposed within the second fin shaped structure.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 6, 2017
From: CHENG, CHI-HSUAN; CHIU, CHENG-PU; SU, YU-CHIH; WANG, CHIH-YI; HSIEH, CHIN-YANG; HSU, TIEN-SHAN; WANG, YAO-JHAN
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 043493/0078 →
Priority Claims (1)
TW 106124194 A · Jul 19, 2017 · national
Continuity (1)
Related Publication 20190027603A1 · Jan 24, 2019