IP Library Granted Patent US 10,347,736
Granted Patent B2
US 10,347,736 · App. 15/697,161 · Granted Jul 9, 2019

High power gallium nitride electronics using miscut substrates

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,347,736
App. No.
15/697,161
Granted
Jul 9, 2019
Kind
B2
Abstract

A method of fabricating an electronic device includes providing a III-V substrate having a hexagonal crystal structure and a normal to a growth surface characterized by a misorientation from the <0001> direction of between 0.15° and 0.65°. The method also includes growing a first III-V epitaxial layer coupled to the III-V substrate and growing a second III-V epitaxial layer coupled to the first III-V epitaxial layer. The method further includes forming a first contact in electrical contact with the III-V substrate and forming a second contact in electrical contact with the second III-V epitaxial layer.

Claims (29)

1. A method of fabricating an electronic device, the method comprising:

providing an n-type GaN substrate having a hexagonal crystal structure and a normal to a growth surface characterized by a misorientation from the <0001> direction of between 0.15° and 0.65°;

growing a first n-type GaN epitaxial layer coupled to the n-type GaN substrate;

growing a second p-type GaN epitaxial layer coupled to the first n-type GaN epitaxial layer;

forming a first contact in electrical contact with the n-type GaN substrate; and

forming a second contact in electrical contact with the second p-type GaN epitaxial layer.

2. The method of claim 1 wherein the normal to the growth surface is misoriented towards the negative <1 1 00> direction.

3. The method of claim 2 wherein the misorientation is between 0.4° and 0.5°.

4. The method of claim 1 wherein the normal to the growth surface is characterized by a misorientation towards the <11 2 0> direction of substantially zero degrees.

5. The method of claim 1 wherein the first n-type GaN epitaxial layer has a thickness greater than 3 μm.

6. The method of claim 5 wherein the first n-type GaN epitaxial layer has a thickness greater than 5 μm.

7. The method of claim 1 wherein the electronic device comprises a PN diode, the first contact comprises a cathode, and the second contact comprises an anode.

8. The method of claim 1 further comprising forming an isolation region disposed laterally to the second p-type GaN epitaxial layer.

9. The method of claim 1 further comprising forming a third III-V epitaxial layer disposed between the second p-type GaN epitaxial layer and the second contact, wherein a doping density of the third III-V epitaxial layer is higher than a doping density of the second p-type GaN epitaxial layer.

10. A method of fabricating an electronic device, the method comprising:

providing a III-V substrate having a hexagonal crystal structure and a normal to a growth surface characterized by a misorientation from the <0001> direction of between 0.15° and 0.65°;

growing a first III-V epitaxial layer coupled to the III-V substrate;

growing a second III-V epitaxial layer coupled to the first III-V epitaxial layer;

forming a first contact in electrical contact with the III-V substrate; and

forming a second contact in electrical contact with the second III-V epitaxial layer.

11. The method of claim 10 wherein the normal to the growth surface is misoriented towards the negative <1 1 00> direction.

12. The method of claim 11 wherein the misorientation is between 0.4° and 0.5°.

13. The method of claim 10 wherein the normal to the growth surface is characterized by a misorientation towards the <11 2 0> direction of substantially zero degrees.

14. The method of claim 10 wherein the III-V substrate comprises an n-type GaN substrate.

15. The method of claim 10 wherein the first III-V epitaxial layer comprises an n-type GaN epitaxial layer having a thickness greater than 3 μm and the second III-V epitaxial layer comprises a p-type GaN epitaxial layer.

16. The method of claim 15 wherein the n-type GaN epitaxial layer has a thickness greater than 5 μm.

17. The method of claim 10 wherein the electronic device comprises a PN diode, the first contact comprises a cathode of the PN diode, and the second contact comprises an anode.

18. The method of claim 10 further comprising forming an isolation region disposed laterally to the second III-V epitaxial layer.

19. The method of claim 10 further comprising forming a third III-V epitaxial layer disposed between the second III-V epitaxial layer and the second contact, wherein a doping density of the third III-V epitaxial layer is higher than a doping density of the second III-V epitaxial layer.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE THE ASSIGNOR NAME PREVIOUSLY RECORDED AT REEL: 66783 FRAME: 161. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Apr 24, 2024
From: NEXGEN (ASSIGNMENT FOR THE BENEFIT OF CREDITORS), LLC
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 067217/0886 →
NUNC PRO TUNC ASSIGNMENT Recorded Apr 24, 2024
From: NEXGEN POWER SYSTEMS, INC.
To: NEXGEN (ASSIGNMENT FOR THE BENEFIT OF CREDITORS), LLC
Reel/Frame 067852/0662 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 19, 2024
From: NEXGEN POWER SYSTEMS, INC.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 067172/0711 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 11, 2024
From: NEXGEN POWER SYSTEMS, INC.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 066783/0161 →
RELEASE OF SECURITY INTEREST Recorded Jul 26, 2021
From: SOUTH LAKE ONE LLC
To: NEXGEN POWER SYSTEMS, INC.
Reel/Frame 056973/0477 →
SECURITY INTEREST Recorded Oct 23, 2020
From: NEXGEN POWER SYSTEMS, INC.
To: SOUTH LAKE ONE LLC
Reel/Frame 054244/0822 →