IP Library › Granted Patent US 10,600,896
Granted Patent B2
US 10,600,896 · App. 15/700,337 · Granted Mar 24, 2020

Semiconductor device and method for producing the same

Inventors: Takamitsu Matsuo (Hitachinaka, JP); Hitoshi Matsuura (Hitachinaka, JP); Yasuyuki Saito (Hitachinaka, JP); Yoshinori Hoshino (Hitachinaka, JP)
Assignee: Renesas Electronics Corporation
H01L29/7397H01L29/0619H01L29/1095H01L29/407H01L29/4236H01L29/42376H01L29/6634H01L29/66348H01L29/7396H01L29/0696
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Quick Facts
Patent No.
US 10,600,896
App. No.
15/700,337
Granted
Mar 24, 2020
Kind
B2
Abstract

In an active region, a gate electrode is disposed in a trench. Spaced apart from the gate electrode, an emitter electrode is disposed in the trench. A source diffusion layer and a base diffusion layer are formed in the active region. The base diffusion layer has a base bottom portion inclined in such a manner that a portion of the base bottom portion adjacent to the emitter electrode is positionally deeper than a portion of the base bottom portion adjacent to the gate electrode. A contact portion has a contact bottom portion inclined in such a manner that a portion of the contact bottom portion in contact with the emitter electrode is positionally deeper than a portion of the contact bottom portion in contact with the base diffusion layer.

Claims (56)

1. A semiconductor device comprising a trench gate bipolar transistor, comprising:

a semiconductor substrate of a first conductivity type having a first surface;

a first region and a second region defined in the semiconductor substrate adjacent to each other;

a gate electrode formed in a first trench extending from the first surface of the semiconductor substrate located in the first region to a first depth, with a first insulating film interposed;

an emitter electrode formed in a second trench extending from the first surface to the first depth, with a second insulating film interposed, such that the emitter electrode is spaced from the gate electrode in such a manner that a region of the semiconductor substrate located in the first region is interposed;

a source region of the first conductivity type formed from the first surface of the semiconductor substrate located in the first region between the gate electrode and the emitter electrode to a second depth shallower than the first depth;

a base region of a second conductivity type formed from the second depth of the semiconductor substrate located in the first region between the gate electrode and the emitter electrode to a position deeper than the second depth and shallower than the first depth;

a floating region of the second conductivity type formed from the first surface of the semiconductor substrate located in the second region to a position deeper than the first depth; and

a contact portion electrically connected to the emitter electrode, the source region, and the base region,

the contact portion being formed in a manner astride the emitter electrode and the base region,

the contact portion having a contact bottom portion inclined in such a manner that a first portion of the contact bottom portion in contact with the emitter electrode is positionally deeper than a second portion of the contact bottom portion in contact with the base region.

2. The semiconductor device according to claim 1 , wherein:

the base region has a base bottom portion inclined in such a manner that a first portion of the base bottom portion adjacent to the emitter electrode is positionally deeper than a second portion of the base bottom portion adjacent to the gate electrode; and

a length from the second portion of the base bottom portion to a lower end of the gate electrode is longer than a length from the first portion of the base bottom portion to the lower end of the gate electrode.

3. The semiconductor device according to claim 1 , wherein:

the contact portion has the contact bottom portion in contact with the emitter electrode and the base region; and

the contact portion has a contact side portion in contact with the source region and the base region.

4. A semiconductor device comprising a trench gate bipolar transistor, comprising:

a semiconductor substrate of a first conductivity type having a first surface;

a first region and a second region defined in the semiconductor substrate adjacent to each other;

a gate electrode formed in a first trench extending from the first surface of the semiconductor substrate located in the first region to a first depth, with a first insulating film interposed;

a source region of the first conductivity type formed from the first surface of the semiconductor substrate located between the gate electrode and the second region to a second depth shallower than the first depth;

a base region of a second conductivity type formed from the second depth of the semiconductor substrate located between the gate electrode and the second region to a position deeper than the second depth;

a carrier passage preventing portion including an emitter electrode and preventing a carrier from flowing therethrough, the carrier passage preventing portion being formed in a region of the semiconductor substrate located in the second region such that the carrier passage preventing portion is spaced from the gate electrode in such a manner that a region of the semiconductor substrate located in the first region is interposed; and

a contact portion electrically connected to the emitter electrode, the source region, and the base region,

the contact portion having a bottom portion in contact with the emitter electrode,

the contact portion having a contact side portion in contact with the source region and the base region,

wherein:

the carrier passage preventing portion includes the emitter electrode and a floating region of a second conductivity type;

the emitter electrode is formed in a second trench extending from the first surface to the first depth, with a second insulating film interposed, such that the emitter electrode is spaced from the gate electrode in such a manner that a region of the semiconductor substrate located in the first region is interposed; and

the floating region is formed from the first surface of the semiconductor substrate located in the second region to a position deeper than the first depth, and

wherein:

the base region has a base bottom portion inclined in such a manner that a first portion of the base bottom portion adjacent to the emitter electrode is positionally deeper than a second portion of the base bottom portion adjacent to the gate electrode; and

a length from the second portion of the base bottom portion to a lower end of the gate electrode is longer than a length from the first portion of the base bottom portion to the lower end of the gate electrode.

5. The semiconductor device according to claim 4 , wherein an upper end of the emitter electrode is lower in level than an upper end of the gate electrode.

6. The semiconductor device according to claim 4 , wherein the emitter electrode is larger in width than the gate electrode.

7. The semiconductor device according to claim 4 , wherein:

the carrier passage preventing portion is the emitter electrode; and

the emitter electrode is formed in a second trench extending from the first surface of the semiconductor substrate located throughout the second region to the first depth, with a second insulating film interposed.

8. The semiconductor device according to claim 7 , wherein an upper end of the emitter electrode is lower in level than an upper end of the gate electrode.

9. A semiconductor device comprising a trench gate bipolar transistor, comprising:

a semiconductor substrate of a first conductivity type having a first surface;

a first region and a second region defined in the semiconductor substrate adjacent to each other;

a gate electrode formed in a first trench extending from the first surface of the semiconductor substrate located in the first region to a first depth, with a first insulating film interposed;

a source region of the first conductivity type formed from the first surface of the semiconductor substrate located between the gate electrode and the second region to a second depth shallower than the first depth;

a base region of a second conductivity type formed from the second depth of the semiconductor substrate located between the gate electrode and the second region to a position deeper than the second depth;

a carrier passage preventing portion including an emitter electrode and preventing a carrier from flowing therethrough, the carrier passage preventing portion being formed in a region of the semiconductor substrate located in the second region such that the carrier passage preventing portion is spaced from the gate electrode in such a manner that a region of the semiconductor substrate located in the first region is interposed; and

a contact portion electrically connected to the emitter electrode, the source region, and the base region,

the contact portion having a bottom portion in contact with the emitter electrode,

the contact portion having a contact side portion in contact with the source region and the base region,

wherein:

the carrier passage preventing portion is the emitter electrode; and

the emitter electrode is formed in a second trench extending from the first surface of the semiconductor substrate located throughout the second region to the first depth, with a second insulating film interposed, and

wherein:

the base region has a base bottom portion inclined in such a manner that a first portion of the base bottom portion adjacent to the emitter electrode is positionally deeper than a second portion of the base bottom portion adjacent to the gate electrode; and

a length from the second portion of the base bottom portion to a lower end of the gate electrode is longer than a length from the first portion of the base bottom portion to the lower end of the gate electrode.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2017
From: MATSUO, TAKAMITSU; MATSUURA, HITOSHI; SAITO, YASUYUKI; HOSHINO, YOSHINORI
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 043543/0146 →
Priority Claims (1)
JP 2016-177746 · Sep 12, 2016 · national
Continuity (1)
Related Publication 20180076308A1 · Mar 15, 2018
Cited By (2)
US 12,426,248 US 12,550,400