Signal pairing for module expansion of a failsafe computing system
A system includes a central processing unit (CPU), a first input/output (I/O) module, and a second I/O module. The first I/O module includes a first module health controller operatively connected to the CPU. The second I/O module includes a second module health controller operatively connected to the first module health controller and the CPU. One of the first module health controller and the second module health controller is configured to assert a paired module health signal to the CPU indicating that the first I/O module and the second I/O module are health.
1. A system comprising:
a central processing unit (CPU);
a first input/output (I/O) module comprising a first module health controller operatively connected to the CPU; and
a second I/O module comprising a second module health controller operatively connected to the first module health controller and the CPU,
wherein the first module health controller and the second module health controller are configured to assert a paired module health signal to the CPU indicating that the first I/O module and the second I/O module are healthy, and
wherein the first I/O module and the second I/O module communicate at least one of a peer module present output (PMPO) signal, a peer module present input (PMPI) signal, a module health pair output (MHPO) signal, and a module health pair input (MHPI) signal therebetween.
2. The system of claim 1 , wherein the asserted paired module health signal comprises a repeating, predefined bit pattern.
3. The system of claim 1 , wherein the CPU is configured to place the first I/O module and the second I/O module in one of the following states upon reception of the asserted paired module health signal: an active state or a standby state.
4. The system of claim 1 , wherein one of the first module health controller and the second module health controller is configured to de-assert the paired module health signal if at least one of the first I/O module and the second I/O module is unhealthy.
5. The system of claim 4 , wherein the de-asserted paired module health signal comprises a low signal.
6. The system of claim 4 , wherein the CPU is configured to place the first I/O module and the second I/O module in a failsafe state upon reception of the de-asserted paired module health signal.
7. The system of claim 1 , further comprising:
a backplane operatively connected to the first module health controller, the second module health controller, and the CPU,
wherein the backplane is configured to transmit the at least one PMPO, PMPI, MHPO, and MHPI signals between the first module health controller and the second module health controller.
8. The system of claim 1 , wherein each of the first module health controller and second module health controller is configured to receive a PAIR signal indicating whether the first I/O module and second I/O module should assert their respective health statuses individually or in paired fashion.
9. A method comprising:
receiving, by a first input/output (I/O) module, a PAIR signal indicating whether the first I/O module should assert a paired module health signal or an individual module health signal;
in response to the PAIR signal indicating that the first I/O module should assert the paired module health signal, asserting, by the first I/O module, the paired module health signal; and
in response to the PAIR signal indicating that the first I/O module should assert the individual module health signal, asserting, by the first I/O module, the individual module health signal,
wherein the paired module health signal indicates a module health of both the first I/O module and a second I/O module operatively connected to the first I/O module, and
wherein the individual module health signal indicates a module health of only the first I/O module.
10. The method of claim 9 , further comprising:
in response to the first I/O module asserting the paired module health signal, placing the first I/O module and the second I/O module in one of the following states: an active state or a standby state.
11. The method of claim 9 , wherein the asserted paired module healthy signal comprises a repeating, predefined bit pattern.
12. The method of claim 9 , further comprising:
de-asserting, by the first I/O module, the paired module health signal in response to determining that at least one of the first I/O module and the second I/O module is unhealthy.
13. The method of claim 12 , wherein the de-asserted paired module health signal comprises a low signal.
14. The method of claim 12 , further comprising:
in response to the first I/O module de-asserting the paired module health signal, placing the first I/O module and the second I/O module in a failsafe state.
15. The method of claim 9 , further comprising:
transmitting signals between the first I/O module and the second I/O module.
16. The method of claim 15 , wherein the signals comprise at least one of:
a peer module present output (PMPO) signal;
a peer module present input (PMPI) signal;
a module health pair output (MHPO) signal; and
a module health pair input (MHPI) signal.
17. The method of claim 9 , further comprising:
in response to the first I/O module asserting the individual module health signal, placing the first I/O module in one of the following states: an active state or a standby state.
18. The method of claim 17 , wherein the asserted individual module health signal comprises a repeating, predefined bit pattern.