Switch with local silicon on insulator (SOI) and deep trench isolation
The present disclosure relates to semiconductor structures and, more particularly, to a switch with local silicon on insulator (SOI) and deep trench isolation structures and methods of manufacture. The structure a structure comprises an air gap located under a device region and bounded by an upper etch stop layer and deep trench isolation structures.
1. A structure comprising:
a semiconductor substrate material;
an etch stop layer on an upper surface of the semiconductor substrate material;
an epitaxial material on the etch stop layer;
a device region over the epitaxial material, the device region including one or more devices;
a deep trench isolation structure surrounding the device region, extending into the semiconductor substrate material; and
a cavity within the semiconductor substrate material and under the device region, and bounded by a layer of insulator material or poly/insulator material and the etch stop layer between an epitaxial semiconductor layer and the semiconductor substrate material and on a top of the cavity and further completely surrounded by the deep trench isolation structure on all sides, the deep trench isolation structure at least partially lined with the layer of insulator material or poly/insulator material, and the etch stop layer being directly on the layer of insulator material or poly/insulator material and a top surface of the semiconductor substrate material,
wherein the layer of insulator material or poly/insulator material bounds sidewalls of the air gap, and
sidewalls of the deep trench isolation structures are in direct contact with sidewalls of the layer of insulator material or poly/insulator material.
2. The structure of claim 1 , wherein the etch stop layer is SiGe and is selective to the semiconductor material.
3. The structure of claim 1 , wherein the semiconductor substrate material is a high resistivity wafer.
4. The structure of claim 1 , wherein the deep trench isolation structure extends into the semiconductor substrate material to a depth below a bottom surface of the cavity.
5. The structure of claim 1 , further comprising a well region above the cavity, the one or more devices being formed over the well region, and the well region is a n-doped well.
6. The structure of claim 1 , further comprising at least one vent via aligned with the cavity and the deep trench isolation structure, which is filled with material, and the at least one vent via is lined with a nitride material.
7. The structure of claim 1 , wherein the cavity is lined with a deposited material comprising oxide/poly silicon material.
8. The structure of claim 1 , further comprising vias aligned on sides of the cavity, wherein the vias extend beyond the etch stop layer and filled with material, the cavity is filled with the same material with a pinch-off air gap formed within the material within the cavity, the pinch-off air gap is under a device above the etch stop layer, the cavity and the deep trench isolation structure are located within a same layer of the same semiconductor substrate material, the vias are lined with a nitride material, and contacts are formed in direct contact with silicide regions of the device.