IP Library › Granted Patent US 10,115,680
Granted Patent B2
US 10,115,680 · App. 15/703,333 · Granted Oct 30, 2018

Semiconductor memory device and method for manufacturing the same

Inventor: Takeshi Kusakabe (Yokkaichi, JP)
Assignee: Toshiba Memory Corporation
H01L23/562H01L23/544H01L27/1157H01L27/11565H01L27/11582H01L2223/54426
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Quick Facts
Patent No.
US 10,115,680
App. No.
15/703,333
Granted
Oct 30, 2018
Kind
B2
Abstract

According to an embodiment, a semiconductor memory device includes a substrate, a first stacked body, a columnar part, a second insulating film, and a second stacked body. The first stacked body is provided in a first region on the substrate. The second insulating film is provided in a second region on the substrate, and has a first thickness in a stacking direction of the first stacked body. The second stacked body is provided on the second insulating film. The second stacked body includes a first film and a third insulating film stacked alternately on one another. The uppermost first film in the first films of the second stacked body is located at a first distance in the stacking direction from the upper surface of the substrate. The first thickness is a thickness not less than 30 percent of the first distance.

Claims (70)

1. A semiconductor memory device comprising:

a substrate;

a first stacked body provided in a first region on the substrate, and including a first insulating film and an electrode film stacked alternately on one another;

a columnar part provided in the first stacked body, extending in a stacking direction of the first stacked body, and including a connection part widened in width in a first direction along an upper surface of the substrate;

a second insulating film provided in a second region on the substrate, and having a first thickness in the stacking direction; and

a second stacked body provided on the second insulating film, and including a first film and a third insulating film stacked alternately on one another,

an uppermost first film in the second stacked body being located at a first distance in the stacking direction from the upper surface of the substrate, and

the first thickness is not less than 30 percent of the first distance.

2. The device according to claim 1 , wherein

the second stacked body has a second thickness in the stacking direction from a lowermost layer to the uppermost first film in the first films, and

the second thickness is not less than 30 percent of the first distance.

3. The device according to claim 1 , further comprising:

a columnar member provided in the second insulating film, and extending in the stacking direction.

4. The device according to claim 3 , wherein

the columnar member includes a columnar member material which is different from a first film material and a third insulating film material.

5. The device according to claim 3 , wherein

the columnar member includes silicon.

6. The device according to claim 3 , wherein

the columnar member includes a widened part widened in width in the first direction, and

an upper surface of the connection part is located on substantially a same plane as an upper surface of the widened part.

7. The device according to claim 3 , wherein

an upper surface of the columnar member is located above an upper surface of the second insulating film, and

the second stacked body is provided with a step.

8. The device according to claim 1 , wherein

the first insulating film and the third insulating film include silicon oxide, and

the first film includes silicon nitride.

9. The device according to claim 1 , wherein

the first stacked body includes a third stacked body and a fourth stacked body, the connection part of the columnar part being located in the third stacked body, the fourth stacked body being provided on the third stacked body,

the columnar part includes a channel and a charge storage film provided on a side surface of the channel.

10. The device according to claim 1 , wherein

the second region is provided on a periphery of the first region, and

a third region is located between the first region and the second region on the substrate, a peripheral circuit being provided in the third region.

11. A semiconductor memory device comprising:

a substrate;

a first stacked body provided in a first region on the substrate, and including a first insulating film and an electrode film stacked alternately on one another;

a columnar part provided in the first stacked body, and extending in a stacking direction of the first stacked body;

a second insulating film provided in a second region on the substrate, and having a first thickness in the stacking direction; and

a second stacked body provided on the second insulating film, and including a first film and a third insulating film stacked alternately on one another,

an uppermost first film of the second stacked body being located at a first distance in the stacking direction from an upper surface of the substrate, and

the first thickness is not less than 30 percent of the first distance.

12. The device according to claim 11 , wherein

the second stacked body has a second thickness in the stacking direction from a lowermost layer to an uppermost first film, and

the second thickness is not less than 30 percent of the first distance.

13. The device according to claim 11 , further comprising:

a columnar member provided in the second insulating film, and extending in the stacking direction.

14. The device according to claim 13 , wherein

the columnar member includes a columnar member material which is different from a first film material and a third insulating film material.

15. The device according to claim 13 , wherein

the columnar member includes silicon.

16. The device according to claim 13 , wherein

an upper surface of the columnar member is located above an upper surface of the second insulating film, and

the second stacked body is provided with a step.

17. The device according to claim 11 , wherein

the first insulating film and the third insulating film include silicon oxide, and

the first film includes silicon nitride.

18. The device according to claim 11 , wherein

the columnar part has a channel and a charge storage film provided on a side surface of the channel.

19. A method for manufacturing a semiconductor memory device, comprising:

forming a first stacked body by alternately stacking a first insulating film and a first film in each of a first region and a second region on a substrate;

forming a hollow in the second region by removing the first stacked body in the second region;

forming a second insulating film in the hollow in the second region;

forming a plurality of first through holes extending in a stacking direction of the first stacked body in the first stacked body in each of the first region and the second region;

widening a width of an upper part of each of the first through holes by partially removing the first insulating film of an uppermost layer of the first stacked body in the first region, and partially removing the second insulating film in the second region;

forming second films in the plurality of first through holes;

exposing upper parts of the second films by partially removing the second insulating film in the second region;

forming a second stacked body having a step in the second region by alternately stacking a third insulating film and a third film on the first stacked body and the second films in the first region, and on the second insulating film and the second film in the second region; and

forming a plurality of second through holes extending in the stacking direction and located on the plurality of first through holes in the second stacked body in the first region based on the step in the second region.

20. The method according to claim 19 , further comprising:

forming a plurality of third through holes extending in the stacking direction in the first stacked body and the second stacked body by removing the second films in the plurality of first through holes via the plurality of second through holes; and

forming semiconductor layers in the third through holes.

Assignments (4)
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 27, 2017
From: KUSAKABE, TAKESHI
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043964/0880 →
Priority Claims (1)
JP 2017-056413 · Mar 22, 2017 · national
Continuity (1)
Related Publication 20180277494A1 · Sep 27, 2018
Cited By (2)
US 12,482,774 US 12,625,440