Semiconductor structure body and method for manufacturing semiconductor structure body with alignment between stories of the same
A semiconductor structure body of an embodiment includes a stacked body. In the stacked body, a plurality of conductive layers and a plurality of insulating layers are alternately stacked, and a plurality of through holes penetrating the conductive layers and the insulating layers in the stacking direction are provided. In the interior of the stacked body, in a region corresponding to an identical pair of coordinates in a planar coordinate system intersecting the stacking direction, a plurality of identical alignment marks or deviation measurement marks are formed, with one or more stories each including a predetermined number of conductive layers and a predetermined number of insulating layers interposed therebetween.
1 . A semiconductor structure body
comprising a stacked body with multiple stories in each of which a plurality of conductive layers and a plurality of insulating layers are alternately stacked, the stacked body including a plurality of through holes penetrating the conductive layers and the insulating layers in a stacking direction, wherein,
the multiple stories of the stacked body is four stories or more,
the stacked body includes, in a region corresponding to an identical pair of coordinates in a planar coordinate system intersecting the stacking direction, a plurality of identical alignment marks or deviation measurement marks, and
the identical alignment marks or the deviation measurement marks are placed in a region corresponding to a first pair of coordinates on an uppermost surface of an N-th story (N is an integer equal to or larger than 2) of the multiple stories and a region corresponding to the first pair of coordinates on an uppermost surface of an (N+2)-th story of the multiple stories.
2 . The semiconductor structure body according to claim 1 , wherein
the identical alignment marks or the deviation measurement marks are placed in a region corresponding to a second pair of coordinates on an uppermost surface of an (N+1)-th story of the multiple stories and a region corresponding to the second pair of coordinates on an uppermost surface of an (N+3)-th story of the multiple stories.
3 . The semiconductor structure body according to claim 1 , wherein
the identical alignment marks or the deviation measurement marks are each formed by a process in which a level difference formed by reducing a thickness of at least one of the conductive layer and the insulating layer propagates to an uppermost surface of the respective story, and
a width of the level difference is 1 μm or more and 4 μm or less.
4 . The semiconductor structure body according to claim 1 , comprising:
a plurality of chip regions; and
a dicing region formed to surround a periphery of each of the chip regions, wherein
the identical alignment marks or the deviation measurement marks are each placed in the dicing region.
5 . The semiconductor structure body according to claim 4 , wherein
the identical alignment marks are each placed in a central portion of a shot region including the plurality of chip regions, or
the deviation measurement marks are each placed in an outer edge portion of the shot region.
6 . The semiconductor structure body according to claim 4 , wherein
a three-dimensional stacked semiconductor memory device is formed in the chip region.
7 . A semiconductor structure body
comprising a stacked body with multiple stories in each of which a plurality of conductive layers and a plurality of insulating layers are alternately stacked, the stacked body including a plurality of through holes penetrating the conductive layers and the insulating layers in a stacking direction, wherein,
the multiple stories of the stacked body is five stories or more,
the stacked body includes, in a region corresponding to an identical pair of coordinates in a planar coordinate system intersecting the stacking direction, a plurality of identical alignment marks or deviation measurement marks, and
the identical alignment marks or the deviation measurement marks are placed in a region corresponding to a first pair of coordinates on an uppermost surface of an N-th story (N is an integer equal to or larger than 2) of the multiple stories and a region corresponding to the first pair of coordinates on an uppermost surface of an (N+3)-th story of the multiple stories.
8 . The semiconductor structure body according to claim 7 , wherein
the identical alignment marks or the deviation measurement marks are placed in a region corresponding to a second pair of coordinates on an uppermost surface of an (N+1)-th story of the multiple stories and a region corresponding to the second pair of coordinates on an uppermost surface of an (N+4)-th story of the multiple stories, and
the identical alignment marks or the deviation measurement marks are placed in a region corresponding to a third pair of coordinates on an uppermost surface of an (N+2)-th story of the multiple stories and a region corresponding to the third pair of coordinates on an uppermost surface of an (N+5)-th story of the multiple stories.