Method of forming vertical FinFET device having self-aligned contacts
A vertical FinFET includes a semiconductor fin formed over a semiconductor substrate. A self-aligned first source/drain contact is electrically separated from a second source/drain contact by a spacer layer that is formed over an endwall of the fin. The spacer layer, which comprises a dielectric material, allows the self-aligned first source/drain contact to be located in close proximity to an endwall of the fin and the associated second source/drain contact without risk of an electrical short between the adjacent contacts.
1. A method of forming a vertical FinFET device, comprising:
etching an opening in a hard mask disposed over a semiconductor fin, the opening extending through a portion of the semiconductor fin to expose an endwall of the semiconductor fin and a top surface of a bottom source/drain region disposed laterally adjacent to the endwall;
forming a sidewall spacer within the opening, wherein the sidewall spacer is formed over the exposed endwall of the semiconductor fin;
forming a top source/drain region over an upper portion of the semiconductor fin and a top source/drain metallization layer over the top source/drain region; and
forming a bottom source/drain metallization layer over the bottom source drain region within the opening, wherein the sidewall spacer is disposed between the top source/drain metallization layer and the bottom source/drain metallization layer.
2. The method of claim 1 , wherein the sidewall spacer thickness ranges from 4 to 20 nm.
3. The method of claim 1 , wherein the sidewall spacer is formed over the entire exposed endwall surface of the fin.
4. The method of claim 1 , wherein the sidewall spacer is formed within the opening over a sidewall surface of the hard mask.
5. The method of claim 1 , wherein the sidewall spacer comprises a material selected from the group consisting of silicon nitride, silicon oxynitride, SiOC, SiOCN and SiBCN.
6. A method of forming a vertical FinFET device, comprising:
forming a hard mask over a semiconductor substrate;
forming a fin over the semiconductor substrate using the hard mask as an etch mask;
forming a bottom source/drain region over the semiconductor substrate, where a lower portion of the fin is in contact with the bottom source/drain region;
forming a gate stack over sidewalls of the fin, the gate stack extending laterally over the bottom source/drain region on at least one side of the fin, wherein the gate stack comprises a gate dielectric and a gate conductor formed over the gate dielectric;
etching an opening in the hard mask and through a portion of the fin to expose an endwall of the fin and a top surface of the bottom source/drain region laterally adjacent to the endwall;
forming a sidewall spacer within the opening, wherein the sidewall spacer is formed over the exposed endwall of the fin;
forming a top source/drain region over an upper portion of the fin and a top source/drain metallization layer over the top source/drain region; and
forming a bottom source/drain metallization layer over the bottom source drain region, wherein the top source/drain metallization layer is formed over a first side of the sidewall spacer and the bottom source/drain metallization layer is formed over a second side of the sidewall spacer opposite to the first side.
7. The method of claim 6 , further comprising forming a bottom spacer over the bottom source/drain region laterally adjacent to the fin prior to forming the gate stack.
8. The method of claim 6 , further comprising etching the gate stack to recess the gate stack to a height below a top surface of the fin.
9. The method of claim 6 , wherein the sidewall spacer is formed directly over the exposed endwall of the fin.
10. The method of claim 6 , wherein the sidewall spacer thickness is 4 to 20 nm.
11. The method of claim 6 , wherein the sidewall spacer is formed over the entire exposed endwall surface of the fin.
12. The method of claim 6 , wherein the sidewall spacer is formed within the opening over a sidewall surface of the hard mask.
13. The method of claim 6 , wherein the sidewall spacer is formed over exposed surfaces of the gate stack within the opening.
14. The method of claim 6 , wherein forming the top source/drain region comprises removing the hard mask to expose a top surface of the fin.
15. The method of claim 6 , wherein a distance between a sidewall of the bottom source/drain metallization layer and the endwall of the fin is 4 to 20 nm.
16. The method of claim 6 , further comprising forming a gate metallization layer in electrical contact with the gate conductor.