IP Library › Granted Patent US 10,164,001
Granted Patent B1
US 10,164,001 · App. 15/707,240 · Granted Dec 25, 2018

Semiconductor structure having integrated inductor therein

Inventors: Ming-Che Lee (Tainan, TW); I-Nan Chen (Taipei, TW); Sheng-Chau Chen (Tainan, TW); Cheng-Hsien Chou (Tainan, TW); Cheng-Yuan Tsai (Hsin-Chu County, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
H01L28/10H01L23/3171H01L23/5227H01L24/05H01L27/01
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Quick Facts
Patent No.
US 10,164,001
App. No.
15/707,240
Granted
Dec 25, 2018
Kind
B1
Abstract

A semiconductor structure includes: a substrate; a first passivation layer over the substrate; a second passivation layer over the first passivation layer; and a magnetic core in the second passivation layer; wherein the magnetic core includes a first magnetic material layer and a second magnetic material layer over the first magnetic material layer, the first magnetic material layer and the second magnetic material layer are separated by a high resistance isolation layer, and the high resistance isolation layer has a resistivity greater than about 1.3 ohm-cm.

Claims (40)

1. A semiconductor structure, comprising:

a substrate;

a first passivation layer over the substrate;

a second passivation layer over the first passivation layer; and

a magnetic core in the second passivation layer;

wherein the magnetic core includes a first magnetic material layer and a second magnetic material layer over the first magnetic material layer, the first magnetic material layer and the second magnetic material layer are separated by a high resistance isolation layer, and the high resistance isolation layer has a resistivity greater than about 1.3 ohm-cm; and

wherein the magnetic core further comprises a metal layer between the high resistance isolation layer and the second magnetic material layer.

2. The semiconductor structure of claim 1 , wherein high resistance isolation layer includes Si 3 N 4 .

3. The semiconductor structure of claim 1 , wherein high resistance isolation layer includes AlN.

4. The semiconductor structure of claim 1 , wherein high resistance isolation layer includes Al 2 O 3 .

5. The semiconductor structure of claim 1 , wherein the metal layer includes tantalum (Ta).

6. The semiconductor structure of claim 1 , wherein the magnetic core further comprises a low resistance isolation layer on a top surface of the second magnetic material layer, and the low resistance isolation layer has a resistivity less than about 1.3 ohm-cm.

7. The semiconductor structure of claim 1 , wherein the magnetic core further comprises another high resistance isolation layer on a top surface of the second magnetic material layer, and the another high resistance isolation layer has a resistivity greater than about 1.3 ohm-cm.

8. A semiconductor structure, comprising:

a first passivation layer;

a second passivation layer over the first passivation layer;

a third passivation layer over the second passivation;

a lower coil segment in the first passivation layer;

an upper coil segment in the third passivation layer; and

a magnetic core in the second passivation layer and insulated from the lower coil segment and the upper coil segment;

wherein the magnetic core includes a first magnetic material layer and a second magnetic material layer over the first magnetic material layer, the first magnetic material layer and the second magnetic material layer are separated by a composite isolation layer including a high resistance isolation layer and a low resistance isolation layer, and the high resistance isolation layer has a resistivity greater than that of the low resistance isolation layer.

9. The semiconductor structure of claim 8 , wherein the high resistance isolation layer is over the low resistance isolation layer.

10. The semiconductor structure of claim 9 , wherein the high resistance isolation layer has a resistivity greater than about 1.3 ohm-cm, and the low resistance isolation layer has a resistivity less than about 1.3 ohm-cm.

11. The semiconductor structure of claim 8 , wherein the magnetic core further comprises a metal layer between the high resistance isolation layer and the second magnetic material layer.

12. The semiconductor structure of claim 8 , wherein the magnetic core further comprises a metal layer below a bottom surface of the first magnetic material layer.

13. The semiconductor structure of claim 8 , wherein the low resistance isolation layer includes oxide of the first magnetic material layer.

14. A semiconductor structure, comprising:

a first passivation layer;

a second passivation layer over the first passivation layer;

a third passivation layer over the second passivation;

a lower coil segment in the first passivation layer;

an upper coil segment in the third passivation layer; and

a magnetic core in the second passivation layer and insulated from the lower coil segment and the upper coil segment;

wherein the magnetic core from bottom to top includes a first magnetic material layer, a second magnetic material layer, a third magnetic material layer and a fourth magnetic material layer, the first magnetic material layer and the second magnetic material layer are separated by a first low resistance isolation layer, the second magnetic material layer and the third magnetic material layer are separated by a high resistance isolation layer, the third magnetic material layer and the fourth magnetic material layer are separated by a second low resistance isolation layer, and the high resistance isolation layer has a resistivity greater than that of the low resistance isolation layer.

15. The method of claim 14 , wherein the high resistance isolation layer has a resistivity greater than about 1.3 ohm-cm, and the low resistance isolation layer has a resistivity less than about 1.3 ohm-cm.

16. The semiconductor structure of claim 14 , wherein the first low resistance isolation layer includes oxide of the first magnetic material layer.

17. The semiconductor structure of claim 14 , wherein the second low resistance isolation layer includes oxide of the third magnetic material layer.

18. The semiconductor structure of claim 14 , wherein high resistance isolation layer includes Si 3 N 4 .

19. The semiconductor structure of claim 14 , wherein high resistance isolation layer includes AlN.

20. The semiconductor structure of claim 14 , wherein high resistance isolation layer includes Al 2 O 3 .

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 2, 2017
From: LEE, MING-CHE; CHEN, I-NAN; CHEN, SHENG-CHAU; CHOU, CHENG-HSIEN; TSAI, CHENG-YUAN
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Reel/Frame 044020/0633 →
Cited By (2)
US 12,500,166 US 12,648,160