OTP memory with high data security
A method of programming electrical fuses reliably is disclosed. If a programming current exceeds a critical current, disruptive mechanisms such as rupture, thermal runaway, decomposition, or melt, can be a dominant programming mechanism such that programming is not be very reliable. Advantageously, by controlled programming where programming current is maintained below the critical current, electromigration can be the sole programming mechanism and, as a result, programming can be deterministic and very reliable. In this method, fuses can be programmed in multiple shots with progressive resistance changes to determine a lower bound that all fuses can be programmed satisfactorily and an upper bound that at least one fuse can be determined failed. If programming within the lower and upper bounds, defects due to programming can be almost zero and, therefore, defects are essentially determined by pre-program defects.
1. An OTP memory, comprising:
a plurality of OTP cells, at least one of the OTP cells including at least:
an OTP element including at least one electrical fuse as an OTP element having a first terminal coupled to a first supply voltage line, the at least one OTP element having a resistance; and
a selector coupled to the OTP element with at least one enable signal coupled to a second and/or a third supply voltage line; and
program logic configured to provide programming the at least one of the OTP cells into a different logic state by applying at least one voltage or current pulses to the at least one of the OTP cells via the first, the second, and/or the third supply voltage lines to turn on the selector and to thereby progressively change the resistance of the at least one of the OTP cells,
wherein the at least one of the OTP cells in a virgin state is lightly programmed but is still converted into a logic virgin state.
2. An OTP memory as recited in claim 1 , wherein the resistance of the at least one of the OTP cells in the virgin state is lightly programmed to less than 300 ohm but is still converted into a logic virgin state.
3. An OTP memory as recited in claim 1 , wherein resistance of the at least one of the OTP cells in the virgin state is lightly programmed to a lightly programmed from an unprogrammed virgin resistance to a lightly programmed resistance that is less than 2-3 times the unprogrammed virgin resistance.
4. An OTP memory as recited in claim 1 , wherein the at least one of the OTP cells is programmed to a resistance that depends on the magnitude of the supply voltages applied and/or the duration or number of the programming pulses.
5. An OTP memory as recited in claim 4 , wherein the resistance of the at least one of the OTP cells in the programmed state is greater than 2K ohm.
6. An OTP memory as recited in claim 4 , wherein the resistance of the at least one of the OTP cells in the programmed state is greater than 1K ohm to enhance data security.
7. An OTP memory as recited in claim 1 , wherein the programming of the at least one of the OTP cells to a logic programmed state randomly programs with different voltages, duration, and/or number of pulses, but regardless of being randomly programmed is still converted into the logic programmed state.
8. An OTP memory as recited in claim 1 , wherein the programming of the at least one of the OTP cells from a virgin state to a lightly programmed state randomly programs with different voltages, duration, and/or number of pulses, but regardless of being randomly lightly programmed is still converted into the logic unprogrammed state.
9. An OTP memory, comprising:
a plurality of OTP cells, at least one of the OTP cells including at least:
an OTP element including at least one electrical fuse as an OTP element having a first terminal coupled to a first supply voltage line, the at least one OTP element having a resistance; and
a selector coupled to the OTP element with at least one enable signal coupled to a second and/or a third supply voltage line; and
program logic configured to provide programming the at least one of the OTP cells into a different logic state by applying at least one voltage or current pulses to the at least one of the OTP cells via the first, the second, and/or the third supply voltage lines to turn on the selector and to thereby progressively change the resistance of the at least one of the OTP cells; and
data security logic to introduce variance in the resistance of the OTP cells,
wherein the data security logic impedes cell current from being measured accurately in logic level determinations by varying currents flowing through the first supply voltage line to scramble the cell current.
10. An electronic system, comprising:
a processor; and
an One-Time Programmable (OTP) memory operatively connected to the processor, the OTP memory including a plurality of OTP cells, at least one of the OTP cells comprising:
an OTP element including at least one electrical fuse as an OTP element having a first terminal coupled to a first supply voltage line, the at least one OTP element having a resistance; and
a selector coupled to the OTP element with at least one enable signal coupled to a second and/or a third supply voltage line; and
program logic configured to provide programming the at least one of the OTP cells into a different logic state by applying at least one voltage or current pulses to the at least one of the OTP cell via the first, the second, and/or the third supply voltage lines to turn on the selector and to thereby progressively change the resistance of the at least one of the OTP cells,
wherein the at least one of the OTP cells in a virgin state is lightly programmed but is still converted into a logic virgin state.
11. An electronic system as recited in claim 10 , wherein the electronic system comprises:
a sensing circuit coupled to the OTP memory and configured to sense the resistance of the at least one of the OTP cells and convert to an associated logic state.
12. An electronic system as recited in claim 10 , wherein the resistance of the at least one of the OTP cells in the virgin state is less than 300 ohm.
13. An electronic system as recited in claim 10 , wherein the at least one of the OTP cells is programmed dependent on magnitude of program voltage applied and/or the duration or number of programming pulses applied.
14. An electronic system as recited in claim 10 , wherein the resistance of the at least one of the OTP cells in the programmed state is greater than 2K ohm.
15. An electronic system as recited in claim 10 , wherein the resistance of the at least one of the OTP cells in the programmed state is greater than 1K ohm to enhance data security.
16. An electronic system as recited in claim 10 , wherein the at least one of the OTP cells in a virgin state is lightly programmed to be less than three (3) times its original resistance, but is still converted into the logic virgin state.
17. An electronic system as recited in claim 10 , wherein the at least one of the OTP cells in a virgin state is at first address where a start of instructions for the processor start and is lightly programmed but is still converted into the logic virgin state.
18. A method of programming OTP memory with high data security, comprising:
providing a plurality of OTP cells, at least one of the OTP cells including at least:
an OTP element including at least one electrical fuse as OTP element having a first terminal coupled to a first supply voltage line; and
a selector coupled to the OTP element with at least one enable signal coupled to a second and/or a third supply voltage line, and
programming the at least one OTP cell into a different logic state by applying at least one voltage or current pulses to the at least one OTP cell via the first, the second, and/or the third supply voltage lines to turn on the selector and to thereby change the OTP cell resistance progressively,
wherein program voltage, program time, and/or program pulses are randomized within suitable respective ranges to program at least one of the selected OTP cells.
19. A method of programming an OTP memory as recited in claim 18 , wherein at least one of the selected OTP cells is a virgin OTP cell, and wherein the virgin OTP cell is programmed but is still verified as a virgin fuse state.
20. A method of programming an OTP memory as recited in claim 18 , wherein the resistance of the at least one OTP elements can be programmed into a desirable resistance by at least:
(i) determining the program voltage and program time to a selected OTP cell;
(ii) applying a pulse with the program voltage and time to the selected cell;
(iii) verifying the resistance of the OTP element by measuring the cell current or logic state;
(iv) applying one more shot to program if the resistance of the OTP element does not reach the desirable level.
21. A One-Time Programmable (OTP) memory, comprising:
an OTP memory block including at least a plurality of OTP cells, at least one of the OTP cells including at least:
an electrical fuse having a first terminal coupled to a first supply voltage line; and
a selector coupled to the electrical fuse and having at least one enable signal coupled to a second and/or a third supply voltage line; and
at least one regulator to regulate an input current provided to the OTP memory block,
wherein the least one of the OTP cells is configured to be programmable by applying voltages to the first, second, and/or the third supply voltage lines to turn on the selector and to thereby change the electrical fuse resistance,
wherein program voltage, program time, and/or program pulses are varied within suitable respective ranges to program at least one of the selected OTP cells.