Method and structure of three-dimensional chip stacking
A method includes placing a first plurality of device dies over a first carrier, with the first plurality of device dies and the first carrier in combination forming a first composite wafer. The first composite wafer is bonded to a second wafer, and the first plurality of device dies is bonded to a second plurality of device dies in the second wafer through hybrid bonding. The method further includes de-bonding the first carrier from the first plurality of device dies, encapsulating the first plurality of device dies in an encapsulating material, and forming an interconnect structure over the first plurality of device dies and the encapsulating material.
1. A package comprising:
a first device die;
a second device die over and bonded to the first device die through hybrid bonding;
an encapsulating material encapsulating the second device die therein; and
an interconnect structure over the second device die, wherein the interconnect structure extends beyond edges of the second device die, and edges of the interconnect structure are co-terminus with respective edges of the first device die.
2. The package of claim 1 , wherein the encapsulating material comprises a molding compound.
3. The package of claim 1 further comprising a through-via penetrating through the encapsulating material, wherein the through-via continuously extends from a top surface of the second device die to a bottom surface of the second device die, with no distinguishable interface between upper portions and lower portions of the through-via.
4. The package of claim 1 , wherein the first device die comprises a first bond pad, and the second device die comprises a second bond pad, and the first bond pad physically contacts both the second bond pad and a surface dielectric layer in the second device die.
5. The package of claim 1 , wherein the encapsulating material is in contact with, and is not bonded to, the first device die.
6. The package of claim 1 further comprising an air gap at an interface between the encapsulating material and the first device die.
7. The package of claim 6 , wherein both the encapsulating material and a surface dielectric layer of the first device die are exposed to the air gap.
8. A package comprising:
a first device die comprising:
a first surface dielectric layer; and
a first bond pad in the first surface dielectric layer;
a second device die over the first device die, the second device die comprising:
a second surface dielectric layer bonded to the first surface dielectric layer; and
a second bond pad in the second surface dielectric layer, the second bond pad being bonded to the first bond pad;
a molding compound continuously extending from a top surface of the second device die to a bottom surface of the second device die, with the second device die in the molding compound, wherein the molding compound has a bottom surface contacting, without bonding to, a top surface of the first device die;
an air gap sealed by the molding compound and the first device die; and
an interconnect structure over the second device die.
9. The package of claim 8 further comprising a through-via penetrating through the molding compound, wherein the interconnect structure is electrically coupled to the through-via.
10. The package of claim 8 , wherein the first device die further comprises a dielectric liner comprising:
portion overlapped by a portion of the first surface dielectric layer; and
sidewall portions contacting opposite sidewalls of the first surface dielectric layer.
11. The package of claim 10 , wherein one of the sidewall portions of the dielectric liner is in contact with the second bond pad.
12. The package of claim 8 wherein both the molding compound and the first device die are exposed to the air gap.
13. The package of claim 8 , wherein no chemical and physical bonds are formed between the molding compound and the first device die.
14. The package of claim 8 , wherein the air gap is at an interface between the first device die and the molding compound.
15. A package comprising:
a first device die;
a second device die over and bonded to the first device die, wherein a first surface dielectric layer in the first device die is directly bonded to a second surface dielectric layer in the second device die, and a first surface conductive feature in the first device die is directly bonded to a second conductive feature in the second device die;
an encapsulating material encapsulating the second device die therein, and a bottom surface of the encapsulating material contacts a top surface of the first device die;
a through-via continuously extending from a top surface of the encapsulating material to a bottom surface of the encapsulating material, wherein the through-via is bonded to the first device die; and
an interconnect structure over the second device die, wherein the interconnect structure is electrically coupled to the through-via.
16. The package of claim 15 , wherein the first device die extends laterally beyond edges of the second device die, and the through-via is bonded to a bond pad in the first device die.
17. The package of claim 15 further comprising an air gap enclosed by the encapsulating material and the first device die.
18. The package of claim 17 , wherein both the encapsulating material and the first device die are exposed to the air gap.
19. The package of claim 15 , wherein edges of the interconnect structure are flush with respective edges of the first device die.
20. The package of claim 15 , wherein a back surface of a substrate of the second device die is in physical contact with the interconnect structure.