Low energy accelerator processor architecture with short parallel instruction word
Methods and apparatus for a low energy accelerator processor architecture with short parallel instruction word. An integrated circuit includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory coupled to the system bus; and a low energy accelerator processor coupled to the system bus and configured to execute instruction words retrieved from a low energy accelerator code memory, the low energy accelerator processor having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, each of the execution units configured to perform operations responsive to op-codes decoded from the retrieved instruction words, wherein the width of the instruction words is equal to the data width N. Additional methods and apparatus are disclosed.
1. A data processor, comprising:
a memory configured to store instruction words;
a system bus coupled to the memory; and
a processor coupled to the system bus and configured to execute the instruction words, and further comprising:
load register;
a destination register;
an operand overload register comprising a flag;
a programmer controller unit configured to retrieve the instruction words from the memory; and
a load store execution unit configured to load data based on the instruction words and store the load data to the load register in the processor;
a multiply execution unit configured to perform multiply operations on the load data based on the instruction words and store a result in the destination register; and
an arithmetic logic unit (ALU) execution unit configured to:
perform butterfly and adder operations on the load data in either floating point or fixed point, wherein performing in either floating point or fixed point is based on the flag in the operand overload register; and
store a result in the destination register.
2. The data processor of claim 1 and further comprising a central processor unit coupled to the system bus.
3. The data processor of claim 1 , wherein the processor is further configured to execute fixed point and floating point computations.
4. The data processor of claim 3 , wherein:
the multiply execution unit configured to perform multiply operations in fixed point and floating point form responsive to an operand overload flag in the operand overload register indicating a floating point operation;
the ALU execution unit is configured to perform butterfly and ADD operations in fixed point responsive to the operand overload flag indicating a floating point operation; and
the processor further comprises an operand overload register outputting the operand overload flag.
5. The data processor of claim 1 , wherein the instruction words have a data width that is less than or equal to 32.
6. The data processor of claim 1 , wherein the ALU execution unit perform butterfly and adder operations in response to an operand overload flag in the operand overload register indicating a floating point operation.