IP Library Granted Patent US 10,551,897
Granted Patent B2
US 10,551,897 · App. 15/719,539 · Granted Feb 4, 2020

Combining presence detect pin with device management bus reset and power disable

Inventors: Myron D. Loewen (Berthoud, CO); Andrew W. Morning-Smith (Vancouver, CA); Anthony M. Constantine (Portland, OR)
Assignee: INTEL CORPORATION
G06F1/3231G06F1/24G06F1/3287G06F3/067G06F3/0625G06F3/0634G06F3/0652G06F13/4282G06F21/79G06F2213/0026
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Quick Facts
Patent No.
US 10,551,897
App. No.
15/719,539
Granted
Feb 4, 2020
Kind
B2
Abstract

Provided are devices, systems and methods relating to controller interactions with storage. One embodiment includes an apparatus comprising a controller for communication with a storage device through a signal line, wherein the controller is configured to detect a first signal on the signal line indicating the presence of the storage device on the signal line, and provide a second signal on the signal line to reset the storage device after a detection that the first signal indicates the presence of the storage device. Other embodiments are described and claimed.

Claims (39)

1. An apparatus comprising:

a controller for communication with a storage device through a signal line;

wherein the controller is configured to:

detect a first signal on the signal line indicating a presence of the storage device on the signal line;

provide a second signal on the signal line to reset the storage device in response to an event, after a detection that the first signal indicates the presence of the storage device, wherein the second signal is held for a first time to reset the storage device; and

wherein the second signal is held for a second time to perform a power down of the storage device.

2. The apparatus of claim 1 , wherein the controller is configured to ignore the presence of the storage device during a time when the controller provides the second signal on the signal line to reset the storage device.

3. The apparatus of claim 1 , further comprising a resistor configured to be in communication with the signal line.

4. The apparatus of claim 3 , further comprising a transistor configured to be in communication with the signal line.

5. A system comprising:

a host;

a controller for communication between the host and a storage device; and

a signal line connecting the controller and the storage device;

wherein the controller is configured to:

detect a first signal on the signal line to indicate a presence of the storage device on the signal line;

provide a second signal on the signal line to reset the storage device in response to an event, after a detection that the first signal indicates the presence of the storage device, wherein the second signal is held for a first time to reset the storage device; and

wherein the second signal is held for a second time to perform a power down of the storage device.

6. The system of claim 5 , wherein the controller is further configured to ignore the presence of the storage device during a time when the controller provides the second signal to reset the storage device.

7. The system of claim 5 , wherein the host includes a first resistor in communication with the signal line, wherein the storage device includes a second resistor in communication with the signal line, and wherein the first resistor has a greater resistance than the second resistor.

8. The system of claim 7 , wherein the host includes a transistor in communication with the signal line.

9. The system of claim 5 , further comprising:

an additional controller for communication between the host and an additional storage device;

an additional signal line to connect the additional controller and the additional storage device;

the additional controller configured to detect a first signal on the additional signal line that indicates a presence of the additional storage device on the additional signal line; and

the additional controller configured to provide a second signal on the additional signal line to reset the additional storage device after a detection that the first signal indicates the presence of the additional storage device.

10. An apparatus comprising:

a storage device for communication with a controller through a signal line;

wherein the storage device is configured so that a first signal is provided on the signal line that indicates a presence of the storage device;

wherein the storage device is configured to receive from the controller a second signal on the signal line to reset the storage device in response to an event, wherein the second signal is held for a first time to reset the storage device; and

wherein the second signal is held for a second time to perform a power down of the storage device.

11. The apparatus of claim 10 , further comprising a resistor in the storage device, the resistor configured to be in communication with the signal line.

12. The storage device of claim 10 , wherein the storage device is configured to power down in response to the signal line holding the second signal for a predetermined amount of time.

13. A method for communicating between a host and a storage device, comprising:

configuring a controller for the host to detect a first signal indicating a presence of the storage device on a signal line between the controller for the host and the storage device;

configuring the controller to reset the storage device in response to an event by providing a second signal on the signal line after detecting the first signal indicating the presence of the storage device, wherein the second signal is held for a first time to reset the storage device; and

configuring the controller so that the second signal is held for a second time to perform a power down of the storage device.

14. The method of claim 13 , further comprising configuring the controller to ignore the presence of the storage device during a time when the controller is providing the second signal to reset the storage device.

15. The method of claim 13 , further comprising configuring the host to include a first resistor in communication with the signal line, and configuring the storage device to include a second resistor in communication with the signal line, wherein the first resistor has a greater resistance than the second resistor.

16. The method of claim 15 , further comprising configuring the host to include a transistor in communication with the signal line.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 17, 2025
From: INTEL CORPORATION
To: SK HYNIX NAND PRODUCT SOLUTIONS CORP. (DBA SOLIDIGM)
Reel/Frame 072792/0592 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 6, 2017
From: LOEWEN, MYRON D.; MORNING-SMITH, ANDREW W.; CONSTANTINE, ANTHONY M.
To: INTEL CORPORATION
Reel/Frame 044723/0684 →
Continuity (2)
Provisional Application 62516606 · Jun 7, 2017
Related Publication 20180356872A1 · Dec 13, 2018
Cited By (1)
US 12,431,200