Semiconductor device and fabrication method thereof

1. A semiconductor device, comprising:

a substrate;

a first dielectric layer on the substrate;

a hard mask layer on the first dielectric layer;

a trench in the hard mask layer and the first dielectric layer;

a first source/drain electrode layer on a sidewall of the trench;

a second dielectric layer on the first source/drain electrode layer in the trench;

a second source/drain electrode layer on the second dielectric layer in the trench, wherein both of the first source/drain electrode layer and the second source/drain electrode layer extend along the sidewall and a bottom of the trench;

a third dielectric layer on the second source/drain electrode layer in the trench;

a two-dimensional (2D) material layer overlying the hard mask layer, the first source/drain electrode layer, the second dielectric layer, the second source/drain electrode layer, and the third dielectric layer;

a gate dielectric layer on the 2D material layer; and

a gate electrode on the gate dielectric layer.

2. The semiconductor device according to claim 1 , wherein the 2D material layer comprises transition metal dichalcogenide, graphene, or boron nitride.

3. The semiconductor device according to claim 1 further comprising:

an etch stop layer between the substrate and the first dielectric layer.

4. The semiconductor device according to claim 3 , wherein the first dielectric layer comprises silicon oxide, and the etch stop layer comprises silicon nitride.

5. The semiconductor device according to claim 3 , wherein the first source/drain electrode layer extends vertically along the sidewall of the trench between the 2D material layer and the etch stop layer.

6. The semiconductor device according to claim 5 , wherein a top surface of the first source/drain electrode layer is in direct contact with the 2D material layer and a bottom surface of the first source/drain electrode layer is in direct contact with the etch stop layer.

7. The semiconductor device according to claim 6 , wherein the top surface of the first source/drain electrode layer, a top surface of the second dielectric layer, a top surface of the second source/drain electrode layer, a top surface of the third dielectric layer, and a top surface of the hard mask layer are coplanar.

8. The semiconductor device according to claim 1 , wherein the first source/drain electrode layer, the second dielectric layer, the second source/drain electrode layer, and the third dielectric layer completely fill up the trench.

9. The semiconductor device according to claim 1 , wherein the first source/drain electrode layer is insulated from the second source/drain electrode layer by the second dielectric layer.

10. The semiconductor device according to claim 9 , wherein the first source/drain electrode layer and the second source/drain electrode layer are ring shaped and are concentrically arranged in the trench around the third dielectric layer.

11. A method for fabricating a semiconductor device, comprising:

providing a substrate having thereon an etch stop layer, a first dielectric layer on the etch stop layer, and a hard mask layer on the first dielectric layer;

forming a trench in the hard mask layer and the first dielectric layer;

forming a first source/drain electrode layer on a sidewall of the trench, wherein the first source/drain electrode layer extends along the sidewall and a bottom of the trench;

forming a second dielectric layer to cover the first source/drain electrode layer in the trench;

forming a second source/drain electrode layer on the second dielectric layer in the trench;

forming a third dielectric layer on the second source/drain electrode layer in the trench;

forming a two-dimensional (2D) material layer overlying the hard mask layer, the first source/drain electrode layer, the second dielectric layer, the second source/drain electrode layer, and the third dielectric layer;

forming a gate dielectric layer on the 2D material layer; and

forming a gate electrode on the gate dielectric layer.

12. The method for fabricating a semiconductor device according to claim 11 further comprising:

planarizing the first source/drain electrode layer, the second dielectric layer, the second source/drain electrode layer, and the third dielectric layer.

13. The method for fabricating a semiconductor device according to claim 11 , wherein the 2D material layer comprises transition metal dichalcogenide, graphene, or boron nitride.

14. The method for fabricating a semiconductor device according to claim 11 , wherein the first dielectric layer comprises silicon oxide, and the etch stop layer comprises silicon nitride.

15. The method for fabricating a semiconductor device according to claim 11 , wherein the first source/drain electrode layer extends vertically along the sidewall of the trench between the 2D material layer and the etch stop layer.

16. The method for fabricating a semiconductor device according to claim 15 , wherein a top surface of the first source/drain electrode layer is in direct contact with the 2D material layer and a bottom surface of the first source/drain electrode layer is in direct contact with the etch stop layer.

17. The method for fabricating a semiconductor device according to claim 16 , wherein the top surface of the first source/drain electrode layer, a top surface of the second dielectric layer, a top surface of the second source/drain electrode layer, a top surface of the third dielectric layer, and a top surface of the hard mask layer are coplanar.

18. The method for fabricating a semiconductor device according to claim 11 , wherein the first source/drain electrode layer, the second dielectric layer, the second source/drain electrode layer, and the third dielectric layer completely fill up the trench.

19. The method for fabricating a semiconductor device according to claim 11 , wherein the first source/drain electrode layer is insulated from the second source/drain electrode layer by the second dielectric layer.

20. The method for fabricating a semiconductor device according to claim 19 , wherein the first source/drain electrode layer and the second source/drain electrode layer are ring shaped and are concentrically arranged in the trench around the third dielectric layer.