Surface mount emissive elements
A surface mount emissive element is provided with a top surface and a bottom surface. A first electrical contact is formed exclusively on the top surface, and a second electrical contact is formed exclusively on the top surface. A post extends from the bottom surface. An emissive display is also provided made from surface mount emissive elements and an emissions substrate. The emissions substrate has a top surface with a first plurality of wells formed in the emissions substrate top surface. Each well has a bottom surface, sidewalls, a first electrical interface formed on the bottom surface, and a second electrical interface formed on the bottom surface. The emissions substrate also includes a matrix of column and row conductive traces forming a first plurality of column/row intersections, where each column/row intersection is associated with a corresponding well. A first plurality of emissive elements populates the wells.
1. A surface mount light emitting diode (SMLED) comprising:
a top surface;
a bottom comprising a globally flat planar surface;
a first electrical contact formed exclusively on the top surface and configured as a ring;
a second electrical contact formed exclusively on the top surface within a first electrical contact ring perimeter;
a single post connected to and extending from the bottom surface
a first semiconductor layer, with a dopant selected from a first group consisting of an n-dopant or a p-dopant;
a second semiconductor layer, with the unselected dopant from the first group;
a multiple quantum well (MQW) layer interposed between the first semiconductor layer and the second semiconductor layer;
wherein the first semiconductor layer and MQW layer are a stack underlying the first electrical contact, in the shape of a ring; and,
wherein the second semiconductor layer has a disk shape with a center portion underlying the second electrical contact.
2. The SMLED of claim 1 wherein the first semiconductor layer and second semiconductor layer are a material selected from the group consisting of gallium nitride (GaN) and aluminum gallium indium phosphide (AlGaInP).
3. The SMLED of claim 1 further comprising:
a moat formed between the first electrical contact ring and the second electrical contact; and,
an electrical insulator filling the moat.
4. A surface mount light emitting diode (SMLED) comprising:
a top surface;
a bottom comprising a globally flat planar surface;
a first electrical contact formed exclusively on the top surface;
a second electrical contact formed exclusively on the top surface;
a single post connected to and extending from the bottom surface;
a first semiconductor layer, with a dopant selected from a first group consisting of an n-dopant or a p-dopant;
a second semiconductor layer, with the unselected dopant from the first group;
a multiple quantum well (MQW) layer interposed between the first semiconductor layer and the second semiconductor layer;
wherein the second electrical contact is configured as a ring;
wherein the second semiconductor layer has a disk shape with a perimeter underlying the second electrical contact ring;
wherein the first electrical contact is formed within a first electrical contact ring perimeter; and,
wherein the first semiconductor layer and MQW layer are a stack underlying the first electrical contact.
5. The SMLED of claim 4 further comprising:
a moat formed between the second electrical contact ring and the first electrical contact; and,
an electrical insulator filling the moat.
6. The SMLED of claim 4 wherein the top surface is a globally flat planar surface.
7. The SMLED of claim 4 wherein the top surface is bi-planar with a first level and a second level;
wherein the first electrical contact is formed on the first level of the top surface; and,
wherein the second electrical contact is formed on the second level of the top surface.
8. The SMLED of claim 4 wherein the first and second electrical contacts are solder-coated.
9. The SMLED of claim 4 wherein the post is an electrically nonconductive material.
10. The SMLED of claim 4 wherein the bottom surface has a disk shape with a disk diameter (d);
wherein the post is centered on the bottom surface with a post diameter (e) and a post height (f);
wherein the ratio of post diameter (e) to the post height (f) is in the range of 30% to 100%; and,
wherein the ratio of the post diameter (e) to the disk diameter (d) is in the range of 10% to 20%.
11. The SMLED of claim 4 wherein the first semiconductor layer and second semiconductor layer are a material selected from the group consisting of gallium nitride (GaN) and aluminum gallium indium phosphide (AlGaInP).
12. A surface mount emissive element disk comprising:
a disk-shaped top surface;
a disk-shaped bottom surface with a disk diameter (d);
a first electrical contact formed exclusively on the top surface;
a second electrical contact formed exclusively on the top surface;
a post connected to and extending from a center of the bottom surface; and
wherein the post has a diameter (e) and a height (f), where the ratio of post diameter (e) to the post height (f) is in the range of 30% to 100%, and where the ratio of the post diameter (e) to the disk diameter (d) is in the range of 10% to 20%.
13. The surface mount emissive element of claim 12 wherein the surface mount element is a surface mount light emitting diode (SMLED) comprising:
a first semiconductor layer, with a dopant selected from a first group consisting of an n-dopant or a p-dopant;
a second semiconductor layer, with the unselected dopant from the first group; and,
a multiple quantum well (MQW) layer interposed between the first semiconductor layer and the second semiconductor layer.
14. The surface mount emissive element of claim 13 wherein the first semiconductor layer and second semiconductor layer are a material selected from the group consisting of gallium nitride (GaN) and aluminum gallium indium phosphide (AlGaInP).
15. The surface mount emissive element of claim 13 wherein the first electrical contact is configured as a ring;
wherein the first semiconductor layer and MQW layer are a stack underlying the first electrical contact, in the shape of a ring;
wherein the second electrical contact is formed within a first electrical contact ring perimeter; and,
wherein the second semiconductor layer has a disk shape with a center portion underlying the second electrical contact.
16. The surface mount emissive element of claim 15 further comprising:
a moat formed between the first electrical contact ring and the second electrical contact; and,
an electrical insulator filling the moat.
17. The surface mount emissive element of claim 13 wherein the second electrical contact is configured as a ring;
wherein the second semiconductor layer has a disk shape with a perimeter underlying the second electrical contact ring;
wherein the first electrical contact is formed within a second electrical contact ring perimeter; and,
wherein the first semiconductor layer and MQW layer are a stack underlying the first electrical contact.
18. The surface mount emissive element of claim 17 further comprising:
a moat formed between the second electrical contact ring and the first electrical contact; and,
an electrical insulator filling the moat.
19. The surface mount emissive element of claim 12 wherein the top surface is a globally flat planar surface.
20. The surface mount emissive element of claim 12 wherein the top surface is bi-planar with a first level and a second level;
wherein the first electrical contact is formed on the first level of the top surface; and,
wherein the second electrical contact is formed on the second level of the top surface.
21. The surface mount emissive element of claim 12 further comprising:
a plurality of posts extending from the bottom surface.
22. The surface mount emissive element of claim 12 wherein the first and second electrical contacts are solder-coated.
23. The surface mount emissive element of claim 12 wherein the post is an electrically nonconductive material.
24. The surface mount emissive element of claim 12 wherein the bottom surface is a globally flat planar surface.
25. A surface mount emissive element comprising:
a top surface;
a bottom surface;
a first electrical contact formed exclusively on the top surface;
a second electrical contact formed exclusively on the top surface;
a post connected to and extending from the bottom surface; and,
wherein the surface mount emissive element has a disk shape, a disk diameter (d), a disk thickness (a), and a disk aspect ratio of d:a that is greater than 4:1.
26. A surface mount light emitting diode (SMLED) comprising:
a disk-shaped top surface;
a disk-shaped bottom surface;
a first electrical contact formed exclusively on the top surface and configured as a ring;
a second electrical contact formed exclusively on the top surface within a first electrical contact ring perimeter;
a post connected to and extending from a center of the bottom surface;
a first semiconductor layer, with a dopant selected from a first group consisting of an n-dopant or a p-dopant;
a second semiconductor layer, with the unselected dopant from the first group; and,
a multiple quantum well (MQW) layer interposed between the first semiconductor layer and the second semiconductor layer;
wherein the first semiconductor layer and MQW layer are a stack underlying the first electrical contact, in the shape of a ring; and,
wherein the second semiconductor layer has a disk shape with a center portion underlying the second electrical contact.
27. The SMLED of claim 26 wherein the first semiconductor layer and second semiconductor layer are a material selected from the group consisting of gallium nitride (GaN) and aluminum gallium indium phosphide (AlGaInP).