Etch profile control of interconnect structures
A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.
1. A method of forming an interconnect structure, the method comprising:
depositing an etch stop layer on a substrate;
depositing a liner on the etch stop layer, the liner comprising an oxygen-doped carbide material;
depositing a metal oxide layer on the liner;
depositing an interlayer dielectric (ILD) layer on the metal oxide layer;
depositing a low temperature oxide layer over the ILD layer;
depositing a capping layer over the low temperature oxide layer, wherein the low temperature oxide layer is deposited at a temperature lower than that of the capping layer; and
forming a via opening in the capping layer.
2. The method of forming the interconnect structure of claim 1 , wherein the forming the via opening in the capping layer comprises:
depositing a photoresist layer on the capping layer; and
etching the capping layer through a pattern in the photoresist layer.
3. The method of forming the interconnect structure of claim 1 , further comprising:
forming another via opening in the ILD layer and on the metal oxide layer; and
etching a portion of the metal oxide layer through the other via opening.
4. The method of forming the interconnect structure of claim 3 , further comprising depositing a conductive material in the other via opening to form a conductive structure.
5. The method of forming the interconnect structure of claim 3 , wherein a sidewall of the other via opening forms an angle with a horizontal axis in a range from about 70° to about 80°.
6. The method of forming the interconnect structure of claim 1 , wherein the capping layer comprises oxide material and the low temperature oxide layer comprises silicon.
7. The method of forming the interconnect structure of claim 1 , wherein the metal oxide layer comprises chromium, aluminum, titanium, tin, zinc, magnesium, or silver.
8. A method of forming a semiconductor structure, the method comprising:
depositing an etch stop layer on a substrate;
depositing a liner on the etch stop layer;
depositing a metal carbide layer on the liner;
depositing an interlayer dielectric (ILD) layer on the metal carbide layer, wherein the etch stop layer, the liner, the metal carbide layer, and the ILD layer form a vertical stack;
forming a trench etch opening over the ILD layer, wherein forming the trench etch opening comprises:
depositing a nitrogen-free dielectric layer on the ILD layer; and
patterning a silicon-based layer and a nitride layer disposed on the nitrogen-free dielectric layer;
depositing a capping layer over the trench etch opening; and
forming a via etch opening over the capping layer.
9. The method of forming the semiconductor structure of claim 8 , further comprising forming a low temperature oxide layer between the capping layer and the trench etch opening, wherein the low temperature oxide layer is deposited at a temperature lower than that of the capping layer.
10. The method of forming the semiconductor structure of claim 8 , further comprising forming first and second silicon-based layers over the trench etch opening and over the capping layer, respectively.
11. The method of forming the semiconductor structure of claim 8 , further comprising forming first and second organic layers over the trench etch opening and over the capping layer, respectively.
12. The method of forming the semiconductor structure of claim 8 , further comprising:
forming a low temperature oxide layer over the trench etch opening; and
forming another via etch opening in the low temperature oxide layer, wherein the other via etch opening has a width smaller than that of the via etch opening.
13. The method of forming the semiconductor structure of claim 8 , wherein the capping layer comprises an oxide material and the substrate comprises conductive structures formed therein.
14. The method of forming the semiconductor structure of claim 8 , further comprising forming a via in the ILD layer and the metal carbide layer.
15. The method of forming the semiconductor structure of claim 8 , further comprising forming a via in the ILD layer, the metal carbide layer, and the etch stop layer.
16. The method of forming the semiconductor structure of claim 8 , wherein the metal carbide layer comprises chromium, aluminum, titanium, tin, zinc, magnesium, or silver.
17. A method, comprising:
depositing a stack over a substrate; wherein the stack comprises:
an etch stop layer disposed on the substrate;
a liner layer on the etch stop layer; and
a metal-containing layer disposed on the liner layer;
depositing a dielectric layer on the stack;
etching the dielectric layer and the stack to form an opening;
disposing an organic layer over the dielectric layer; and
depositing another stack over the organic layer, wherein the other stack comprises:
an oxide layer;
a silicon-based layer; and
a capping layer, comprising silicon oxide, on the silicon-based layer.
18. The method of claim 17 , further comprising:
depositing another organic layer on the other stack; and
etching the other organic layer and the other stack to form another opening, wherein a sidewall angle of the other opening is less than about 83°.
19. The method of claim 17 , wherein the metal-containing layer comprises chromium oxide, aluminum oxide, titanium oxide; tin oxide, zinc oxide, magnesium oxide, silver oxide, nickel oxide, molybdenum oxide, or combinations thereof.
20. The method of claim 8 , wherein depositing the etch stop layer comprises depositing a silicon-based layer, a boron-based layer, or combinations thereof.