Cobalt filling of interconnects in microelectronics
Processes and compositions for electroplating a cobalt deposit onto a semiconductor base structure comprising submicron-sized electrical interconnect features. In the process, a metalizing substrate within the interconnect features is contacted with an electrodeposition composition comprising a source of cobalt ions, an accelerator comprising an organic sulfur compound, an acetylenic suppressor, a buffering agent and water. Electrical current is supplied to the electrolytic composition to deposit cobalt onto the base structure and fill the submicron-sized features with cobalt. The process is effective for superfilling the interconnect features.
1. A process for electroplating a cobalt deposit onto a semiconductor base structure comprising submicron-sized electrical interconnect features, the process comprising the steps of:
a) contacting a metalizing substrate within said sub-micron sized electrical interconnect features with an electrodeposition composition comprising:
a source of cobalt ions;
an acetylenic suppressor, wherein said acetylenic suppressor is either a reaction product of ethoxylated propargyl alcohol and 1,4-butanediol diglycidyl ether or diethylene glycol bis (2-propynyl) ether;
a buffering agent; and
water; and
b) supplying electrical current to the electrodeposition composition to deposit cobalt onto the semiconductor base structure and fill the submicron-sized electrical interconnect features with cobalt;
wherein the electrodeposition composition is free of any further additive that would function as an accelerator.
2. A process as set forth in claim 1 , wherein said electrodeposition composition further comprises an acid.
3. A process as set forth in claim 1 , wherein said electrodeposition composition has a pH between about 1.5 and about 7 or between about 2.5 and about 5.
4. A process as set forth in claim 1 , wherein said electrodeposition composition further comprises a stress reducer, wherein said stress reducer comprises saccharin.
5. A process as set forth in claim 1 , wherein said electrodeposition composition is free of any functional concentration of reducing agents effective to reduce cobaltous ions (Co 2+ ) to metallic cobalt (Co 0 ).
6. A process as set forth in claim 5 wherein the molar ratio of any nickel ions to the cobalt ions and/or the molar ratio of any iron ions to cobalt ions and/or the molar ratio of the sum of nickel ions and iron ions in said composition is not greater than 0.01.
7. A process as set forth in claim 1 , wherein said composition contains no more than about 0.001 vol. % solids.
8. A process as set forth in claim 1 , wherein said composition is free of any functional concentration of solid particulates, or is free of any solid particulates that would be detectable by analytical apparatus or methods used in industrial fabrication of electronics products.
9. A process as set forth in claim 1 , wherein said features comprise cavities in said semiconductor base structure that are superfilled by rapid bottom-up deposition of cobalt, and wherein said semiconductor base structure, including said submicron features, is immersed in said electrodeposition composition during supply of current to said composition.
10. A process as set forth in claim 9 , wherein said submicron electrical interconnect features comprise a plurality of cavities in said semiconductor base structure, each cavity of said plurality having a bottom, sidewall, and top opening, and electrodeposition of cobalt fills the submicron features from the bottom up by rapid bottom-up deposition at a rate of growth in the vertical direction which is greater than a rate of growth in the horizontal direction.
11. A process as set forth in claim 1 , wherein a metalizing substrate comprising a seminal conductive layer is formed on the internal surfaces of the submicron features, wherein the metalizing substrate is contacted with the electrodeposition composition and the electrical current is supplied to the electrodeposition composition to cause electrodeposition of cobalt on the metalizing substrate that fills the submicron features.
12. A process as set forth in claim 1 , wherein the internal tensile stresses in cobalt filling said features is not greater than 500 MPa.
13. A process as set forth in claim 1 , wherein the entry dimension of the submicron interconnect is less than 100 nm, or less than 50 nm, or less than 30 nm, or less than 20 nm, or less than 10 nm, or between 5 and 15 nm.
14. A process as set forth in claim 1 , wherein said submicron interconnects have an aspect ratio of greater than 3:1 or greater than 4:1 or between 4:1 and 10:1.
15. A process as set forth in claim 1 , wherein said submicron interconnects have an aspect ratio of greater than 15:1, or greater than 20:1, or greater than 30:1 or between 10:1 and 50:1.
16. A process according to claim 1 , wherein said electrodeposition composition is
substantially free of any divalent sulfur compounds, and free of any functional concentration of reducing agents effective to reduce cobaltous ions (Co 2+ ) to metallic cobalt (Co 0 ).
17. A process as set forth in claim 1 , wherein the electrodeposition composition comprises 5 to 10 g/L of cobalt ions.
18. A process as set forth in claim 1 , wherein the electrodeposition composition comprises 10 to 50 mg/L of the acetylenic suppressor.
19. A process as set forth in claim 1 , wherein the acetylenic suppressor comprises a reaction product of ethoxylated propargyl alcohol and 1,4-butanediol diglycidyl ether.
20. A process as set forth in claim 1 , wherein the acetylenic suppressor comprises diethylene glycol bis(2-propynyl) ether.