Array substrate, manufacturing method thereof and display device
An array substrate and a manufacturing method thereof, and a display device are provided. The array substrate includes a substrate, and a plurality of pixel units arranged in an array on the substrate, each of the pixel units is provided with a plurality of thin film transistors, each of the pixel units includes a plurality of light emitting units, the plurality of light emitting units are sequentially arranged along a direction perpendicular to a plane where the substrate is located, and disposed at a side of the thin film transistors away from the substrate, each of the light emitting units is connected with one of the thin film transistors, and different ones of the light emitting units are connected to different ones of the thin film transistors.
1. An array substrate, comprising:
a substrate; and
a plurality of pixel units arranged in an array on the substrate,
wherein each of the pixel units is provided with a plurality of thin film transistors, each of the pixel units comprises a plurality of light emitting units, the plurality of light emitting units are sequentially arranged along a direction perpendicular to a plane where the substrate is located, and disposed at a side of the thin film transistors away from the substrate, each of the light emitting units is connected with one of the thin film transistors, and different ones of the light emitting units are connected to different ones of the thin film transistors to control different light emitting units independently; and
wherein different light emitting units are insulated from each other, and different thin film transistors are insulated from each other;
each of the light emitting units comprises a first electrode, a light-emitting layer and a second electrode; and
the different light emitting units do not share adjacent first electrodes or adjacent second electrodes of corresponding different light emitting units.
2. The array substrate according to claim 1 , further comprising:
a barrier wall surrounding each of the pixel units to define a region for forming the light emitting units.
3. The array substrate according to claim 2 , wherein a thickness of the barrier wall gradually decreases along a direction from a position close to the substrate to a position away from the substrate.
4. The array substrate according to claim 2 , wherein at least one of the thin film transistors is formed between the barrier wall and the substrate, and at least one of the light emitting units is connected with a corresponding one of the thin film transistors through a via hole disposed in the barrier wall.
5. The array substrate according to claim 1 , further comprising:
a thin film packaging layer, disposed at a side of each of the light emitting units away from the substrate.
6. The array substrate according to claim 1 , wherein, and the first electrode is connected with a corresponding one of the thin film transistors.
7. An array substrate, comprising:
a substrate; and
a plurality of pixel units arranged in an array on the substrate,
wherein each of the pixel units is provided with a plurality of thin film transistors, each of the pixel units comprises a plurality of light emitting units, the plurality of light emitting units are sequentially arranged along a direction perpendicular to a plane where the substrate is located, and disposed at a side of the thin film transistors away from the substrate, each of the light emitting units is connected with one of the thin film transistors, and different ones of the light emitting units are connected to different ones of the thin film transistors, wherein each of the pixel units comprises three thin film transistors and three light emitting units, and the three light emitting units respectively emit red light, green light, and blue light; and
wherein the three light emitting units are insulated from each other, and different thin film transistors are insulated from each other;
each of the three light emitting units comprises a first electrode, a light-emitting layer, and a second electrode; and
the three light emitting units do not share adjacent first electrodes or adjacent second electrodes of corresponding different light emitting units.
8. The array substrate according to claim 1 , wherein a maximum size of each of the plurality of light emitting units along a direction parallel to the plane where the substrate is located is less than 10 μm.
9. A manufacturing method of an array substrate, comprising:
forming a plurality of pixel units arranged in an array on a substrate;
forming each of the pixel units comprises:
forming a plurality of thin film transistors on the substrate; and
forming a plurality of light emitting units on the plurality of thin film transistors, the plurality of light emitting units are sequentially arranged along a direction perpendicular to a plane where the substrate is located,
wherein each of the light emitting units is connected with one of the thin film transistors, and different ones of the light emitting units are connected to different ones of the thin film transistors to control different light emitting units independently;
wherein different light emitting units are insulated from each other, and different thin film transistors are insulated from each other;
each of the light emitting units comprises a first electrode, a light-emitting layer and a second electrode; and
different light emitting units do not share adjacent first electrodes or adjacent second electrodes of corresponding different light emitting units.
10. The manufacturing method of the array substrate according to claim 9 , further comprising:
after forming the plurality of thin film transistors, forming a barrier wall to define a region for forming the light emitting units,
wherein forming the plurality of light emitting units on the plurality of thin film transistors comprises:
forming at least one layer in at least one of the light emitting units by an evaporation method using the barrier wall as an evaporation mask plate.
11. The manufacturing method of the array substrate according to claim 9 , wherein one of the light emitting units closest to the thin film transistors is formed through an etching method.
12. The manufacturing method of the array substrate according to claim 10 , wherein at least one of the thin film transistors is formed between the barrier wall and the substrate, and the manufacturing method further comprises:
forming a via hole in the barrier wall, and connecting at least one of the light emitting units with a corresponding one of the thin film transistors through the via hole.
13. The manufacturing method of the array substrate according to claim 9 , further comprising:
forming a thin film packaging layer at a side of each of the light emitting units away from the substrate.
14. A display device, comprising the array substrate according to claim 1 .
15. The array substrate according to claim 3 , wherein at least one of the thin film transistors is formed between the barrier wall and the substrate, and at least one of the light emitting units is connected with a corresponding one of the thin film transistors through a via hole disposed in the barrier wall.
16. The manufacturing method of the array substrate according to claim 10 , wherein one of the light emitting units closest to the thin film transistors is formed through an etching method.
17. The array substrate according to claim 15 , wherein the plurality of thin film transistor comprise a first thin film transistor, a second thin film transistor, and a third thin film transistor, the plurality of the light emitting units comprise a first light emitting unit, a second light emitting unit, and a third light emitting unit, and the via hole comprises a first via hole and a second via hole respectively in facing portions of the barrier wall, the first electrode of the first light emitting unit being directly connected with the second thin film transistor, the first electrode of the second light emitting unit being connected with the third thin film transistor through the first via hole in the barrier wall, and the first electrode of the third light emitting unit is connected with the first thin film transistor through the second via hole in the barrier wall.