Methods of forming backside self-aligned vias and structures formed thereby
Methods and structures formed thereby are described, of forming self-aligned contact structures for microelectronic devices. An embodiment includes forming a trench in a source/drain region of a transistor device disposed in a device layer, wherein the device layer is on a substrate, forming a fill material in the trench, forming a source/drain material on the fill material, forming a first source/drain contact on a first side of the source/drain material, and then forming a second source drain contact on a second side of the source/drain material.
1. A microelectronic structure comprising:
a substrate;
a device layer on the substrate;
at least one device within the device layer, wherein the at least one device comprises a gate electrode between a source region and a/drain region;
a first source contact coupled to a first side of the source region;
a first drain contact coupled to a first side of the drain region;
a second source contact coupled to a second side of the source region; and
a second drain contact coupled to a second side of the drain region, wherein the source region and the drain region comprise an epitaxial material, wherein the epitaxial material comprises silicon and germanium.
2. The structure of claim 1 wherein the first source contact and the first drain contact are coupled with a plurality of first interconnects that are below the device layer.
3. The structure of claim 1 wherein the second source contact and the second drain contact are coupled with a plurality of second interconnects that are above the device layer.
4. The structure of claim 1 wherein a fill material is on at least one of the second source contact or the second drain contact.
5. The structure of claim 4 wherein the fill material comprises one or more of titanium, cobalt, tungsten or copper.
6. The structure of claim 4 wherein the fill material further comprises a liner material.
7. The structure of claim 1 wherein the device comprises a non-planar device.
8. A structure comprising:
a substrate;
a fin on the substrate, wherein the fin comprises silicon;
a device layer on the substrate, wherein at least one device is within the device layer, and wherein the at least one device comprises a gate electrode between a source region and a drain region;
a first source contact coupled with a first side of the source region of one of the at least one device, and a first drain contact coupled with a first side of the drain region of one of the at least one device, wherein the first source contact and the first drain contact are coupled with a plurality of lower interconnect structures located below the device layer; and
a second source contact coupled with a second side of the source region and a second drain contact coupled with a second side of the drain regions, wherein the second source contact and the second drain contact are coupled with a plurality of upper interconnect structures that are above the device layer, wherein the source region and the drain region comprise an epitaxial material, wherein the epitaxial material comprises silicon and germanium.
9. The structure of claim 8 wherein the gate electrode is adjacent the first and the second source contact and the first and the second drain contact.
10. The structure of claim 8 wherein a height of the first source contact and the first drain contact and a height of the second source contact and the second drain contact are substantially different from each other.
11. The structure of claim 10 wherein the height of one of the first source and drain contacts or the second source and drain contacts is about twice the height of the other.
12. The structure of claim 8 further comprising a system comprising:
a communication chip communicatively coupled to the structure; and
a DRAM communicatively coupled to the communication chip.
13. The structure of claim 8 further comprising wherein the structure comprises a monolithic 3D device structure.
14. A method of forming a microelectronic structure, comprising:
forming a source trench in a source region and forming a drain trench in a drain region of device layer of a transistor device, wherein the device layer is on a substrate;
forming a fill material in the source trench and in the drain trench;
forming a source material and forming a drain material on the fill material;
forming a first source contact on a first side of the source material, and forming a first drain contact on a first side of the drain material; and
forming a second source contact on a second side of the source material, and forming a second drain contact on a second side of the drain material.
15. The method of claim 14 further comprising wherein the first source contact and the first drain contact are further coupled to a first plurality of interconnects located below the device layer.
16. The method of claim 14 further comprising wherein the second source contact and the second drain contact are coupled to a second plurality of interconnects located above the device layer.
17. The method of claim 14 wherein the fill material comprises a conductive material.
18. The method of claim 14 further comprising wherein the fill material is removed prior to forming the second source contact and the second drain contact.
19. The method of claim 14 , further comprising wherein the second source contact and the second drain contact are formed on the fill material.
20. The method of claim 14 further comprising wherein the device comprises a portion of one of a FINFET, a tri-gate, or a planar transistor structure.
21. The method of claim 14 further comprising wherein the source material and the drain material comprise an epitaxial material.