Semiconductor device including a pad and a wiring line arranged for bringing a probe into contact with the pad and method of manufacturing the same
A semiconductor device having a plurality of wiring layers including a first wiring layer and a second wiring layer, with the first wiring layer being the uppermost layer and including a pad PD that has a first region for bonding a copper wire, and a second region for bringing a probe into contact with the pad. The second wiring layer is one layer below the first wiring layer and includes a first wiring line arranged immediately below the second region of the pad, the second wiring layer having no conductor pattern at a region overlapping with the first region of the pad PD.
1. A semiconductor device comprising:
a semiconductor chip having a pad;
a copper wire electrically connected to the pad of the semiconductor chip; and
a sealing resin portion sealing the semiconductor chip and the copper wire,
wherein the semiconductor chip includes:
a semiconductor substrate; and
a wiring structure formed on a main surface of the semiconductor substrate, the wiring structure including a plurality of insulating films and a plurality of wiring layers,
wherein the plurality of wiring layers includes:
a first wiring layer; and
a second wiring layer,
wherein the first wiring layer is an uppermost layer among the plurality of wiring layers,
wherein the first wiring layer includes the pad,
wherein the pad has:
a first region for bonding the copper wire; and
a second region for bringing a probe into contact with the pad,
wherein the second wiring layer is layer below the first wiring layer,
wherein the second wiring layer includes a first wiring line arranged immediately below the second region of the pad, and
wherein the second wiring layer has no conductor pattern at a region overlapping with the first region of the pad.
2. The semiconductor device according to claim 1 ,
wherein the plurality of wiring layers includes a third wiring layer,
wherein the third wiring layer is one layer below the second wiring layer, and
wherein the third wiring layer includes:
a second wiring line arranged immediately below the first region of the pad; and
a third wiring line arranged immediately below a region other than the first region of the pad.
3. The semiconductor device according to claim 2 ,
wherein the third wiring line is arranged immediately below the second region of the pad.
4. The semiconductor device according to claim 1 ,
wherein the first wiring line is a power supply wiring line or a ground wiring line.
5. The semiconductor device according to claim 1 ,
wherein, in the semiconductor chip, a plurality of the pads is arranged along a first side of an upper surface of the semiconductor chip, and
wherein the first wiring line extends below the plurality of pads.
6. The semiconductor device according to claim 5 ,
wherein the second regions of the plurality of pads are lined in a row in a direction along the first side, and
wherein the first wiring line linearly extends below the second regions of the plurality of pads.
7. The semiconductor device according to claim 6 ,
wherein the first regions of the plurality of pads are lined in a row in the direction along the first side.
8. The semiconductor device according to claim 6 ,
wherein the plurality of pads is formed of mixture of a first pad having the first region closer to the first side than the second region and a second pad having the second region closer to the first side than the first region, and
wherein a distance between the second pad and the first side is larger than a distance between the first pad and the first side.
9. The semiconductor device according to claim 5 ,
wherein the plurality of pads is formed of mixture of a first pad having the first region closer to the first side than the second region and a second pad having the second region closer to the first side than the first region.
10. A semiconductor device comprising:
a semiconductor substrate; and
a wiring structure formed on a main surface of the semiconductor substrate, the wiring structure including a plurality of insulating films and a plurality of wiring layers,
wherein the plurality of wiring layers includes:
a first wiring layer; and
a second wiring layer,
wherein the first wiring is an uppermost layer among the plurality of wiring layers,
wherein the first wiring layer includes a pad,
wherein the pad has:
a first region for bonding the copper wire; and
a second region for bringing a probe into contact with the pad,
wherein the second wiring layer is one layer below the first wiring layer,
wherein the second wiring layer includes a first wiring line arranged immediately below the second region of the pad, and
wherein the second wiring layer has no conductor pattern at a region overlapping with the first region of the pad.
11. The semiconductor device according to claim 10 ,
wherein the plurality of wiring layers includes a third wiring layer,
wherein the third wiring layer is one layer below the second wiring layer, and
wherein the third wiring layer includes:
a second wiring line arranged immediately below the first region of the pad; and
a third wiring line arranged immediately below a region other than the first region of the pad.
12. The semiconductor device according to claim 11 ,
wherein the third wiring line is arranged immediately below the second region of the pad.
13. The semiconductor device according to claim 10 ,
wherein the wiring structure has a first insulating film having an opening at which the first region and the second region of the pad are exposed.
14. A method of manufacturing a semiconductor device comprising the steps of:
(a) preparing a semiconductor substrate;
(b) forming a wiring structure on a main surface of the semiconductor substrate, the wiring structure including a plurality of insulating films and a plurality of wiring layers,
wherein the plurality of wiring layers includes:
a first wiring layer; and
a second wiring layer, and
wherein the first wiring layer is an uppermost layer among the plurality of wiring layers;
(c) performing a probing check by bringing a probe into contact with a pad included in the first wiring layer; and
(d) electrically connecting a copper wire to the pad,
wherein the pad has:
a first region for bonding the copper wire; and
a second region for bringing the probe into contact with the pad,
wherein the second wiring layer is one layer below the first wiring layer,
wherein the second wiring layer includes a first wiring line arranged immediately below the second region of the pad, and
wherein the second wiring layer has no conductor pattern in the same layer as a layer of the first wiring line formed immediately below the first region of the pad.
15. The method of manufacturing the semiconductor device according to claim 14 ,
wherein the plurality of wiring layers includes a third wiring layer,
wherein the third wiring layer is one layer below the second wiring layer, and
wherein the third wiring layer includes:
a second wiring line arranged immediately below the first region of the pad; and
a third wiring line arranged immediately below a region other than the first region of the pad.
16. The method of manufacturing the semiconductor device according to claim 15 ,
wherein the third wiring line is arranged immediately below the second region of the pad.
17. The method of manufacturing the semiconductor device according to claim 14 ,
wherein, in the step (c), a vertical type probe card is used.