IP Library Granted Patent US 11,101,254
Granted Patent B2
US 11,101,254 · App. 15/777,810 · Granted Aug 24, 2021

Flip-chip like integrated passive prepackage for SIP device

Inventors: Zhicheng Ding (Shanghai, CN); Bin Liu (Shanghai, CN)
Assignee: Intel Corporation
H01L25/16H01L22/14H01L24/32H01L24/48H01L24/73H01L24/92H01L25/18H01L25/50H01L25/0657H01L2224/32145H01L2224/32225H01L2224/4809H01L2224/48091H01L2224/48147H01L2224/48227H01L2224/73265H01L2224/92247H01L2225/0651H01L2225/06562H01L2924/00014H01L2924/1433H01L2924/1434H01L2924/15311H01L2924/19103H01L2924/19105
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Quick Facts
Patent No.
US 11,101,254
App. No.
15/777,810
Granted
Aug 24, 2021
Kind
B2
Abstract

A system in package and method for making a system in package. A plurality of passive devices are coupled to an interposer. A molding compound envelopes the plurality of passive devices and defines a platform having a substantially planar surface. The interposer is coupled to a substrate. A plurality of integrated circuit dies are coupled in a stack to the planar surface.

Claims (30)

1. A system in package comprising:

an interposer having a lateral width;

a plurality of passive devices each having a first side and a second side opposite the first side, the first side coupled to the interposer;

a molding compound enveloping the plurality of passive devices and completely covering the second side of each of the plurality of passive devices, the molding compound defining a platform having a substantially planar surface, and the molding compound having a lateral width the same as the lateral width of the interposer;

a substrate to which the interposer is coupled;

an additional passive device coupled directly to the substrate, the additional passive device having a top surface above the substantially planar surface of the molding compound; and

a plurality of integrated circuit dies coupled in a stack to the planar surface, wherein the molding compound electrically isolates the plurality of integrated circuit dies from the plurality of passive devices.

2. The system in package of claim 1 , further comprising:

an application-specific integrated circuit (ASIC) coupled to an opposing surface of the substrate from the interposer.

3. The system in package of claim 1 , further comprising:

a plurality of layers of die attach film (DAF), one layer between the planar surface and a first of the plurality of integrated circuit dies, and one layer between each pair of dies in the stack.

4. The system in package of claim 1 , wherein the stack has a stair-step profile, and wherein the substrate has a wire bonding area adjacent to a bottom step.

5. The system in package of claim 1 , further comprising:

a second plurality of passive devices coupled directly to the substrate, at least some of the passive devices in the second plurality having a z dimension greater than a maximum z dimension of the platform.

6. The system in package of claim 1 , wherein the interposer, first plurality of passive devices, and platform form a free package that is independently testable from the substrate.

7. The system in package of claim 1 , wherein the interposer has fewer than four layers.

8. The system in package of claim 1 , wherein the platform has dimensions in x and y substantially equal to the dimensions of the stack in x and y.

9. The system in package of claim 1 , wherein the interposer comprises: a land grid array.

10. A system comprising:

a system in package including:

an interposer having a lateral width;

a plurality of passive devices each having a first side and a second side opposite the first side, the first side coupled to the interposer;

a molding compound enveloping the plurality of passive devices and completely covering the second side of each of the plurality of passive devices, the molding compound defining a platform having a substantially planar surface, and the molding compound having a lateral width the same as the lateral width of the interposer;

a substrate to which the interposer is coupled;

an additional passive device coupled directly to the substrate, the additional passive device having a top surface above the substantially planar surface of the molding compound; and

a plurality of integrated circuit dies coupled in a stack to the planar surface, wherein the molding compound electrically isolates the plurality of integrated circuit dies from the plurality of passive devices;

a display driven by the system in package; and

a touchscreen interface coupled to the display.

11. The system of claim 10 , further comprising an application-specific integrated circuit (ASIC) coupled to an opposing side of the substrate relative to the interposer.

12. The system of claim 11 wherein the platform has its dimensions in x and y substantially equal to the dimensions in x and y of the integrated die stack.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 18, 2025
From: INTEL CORPORATION
To: SK HYNIX NAND PRODUCT SOLUTIONS CORP. (DBA SOLIDIGM)
Reel/Frame 072890/0413 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 17, 2021
From: DING, ZHICHENG; LIN, BIN
To: INTEL CORPORATION
Reel/Frame 056265/0534 →
Continuity (1)
Related Publication 20180374835A1 · Dec 27, 2018