Systems, methods, and apparatus for memory cells with common source lines

1. A method for operating a memory device, comprising:

providing a first voltage to a first transistor of a first memory cell and a third transistor of a second memory cell, wherein the first and second memory cells are coupled to a common source line;

providing a second voltage to a second transistor of the first memory cell and a fourth transistor of the second memory cell; and

providing a third voltage to the first transistor of the first memory cell and the third transistor of the second memory cell.

2. The method of claim 1 , wherein memory cells of the memory device are arranged in rows and columns, and the first and second memory cells are in a same row but different columns.

3. The method of claim 1 , wherein the first memory cell is selected for an erase operation.

4. The method of claim 1 , wherein the first voltage is provided to the common source line.

5. The method of claim 1 , wherein the first voltage is provided to a drain or p-well of the first and third transistors.

6. The method of claim 1 , wherein the first voltage is in an approximate amplitude range of 2 V to 6 V.

7. The method of claim 1 , wherein the second voltage is provided to select gates of the first and second memory cells, the second voltage being in an approximate amplitude range of 0 V to 4 V.

8. The method of claim 1 , wherein the third voltage is provided to control gates of the first and second memory cells, the third voltage being in an approximate amplitude range of 2 V to 6 V.

9. The method of claim 1 , wherein the first and third voltages have a similar approximate amplitude range but opposite polarities.

10. The method of claim 1 , wherein the first and third transistors are silicon-oxide-nitride-oxide-silicon (SONOS) transistors.

11. A method of reading a memory device, comprising:

selecting a first memory cell of the memory device for a read operation, wherein the first memory cell and a second memory cell are in a same row and different columns, and wherein the first and second memory cells are coupled to a common source line;

providing a first voltage to a first transistor of the first memory cell; and

providing a second voltage to a second transistor of the first memory cell.

12. The method of claim 11 , wherein the first voltage is provided to a drain of the first transistor, the first voltage being in an approximate amplitude range of 0.3 V to 1.5 V.

13. The method of claim 11 , wherein the second voltage is provided to a select gate of the first memory cell, the second voltage being in an approximate amplitude range of 1 V to 4 V.

14. The method of claim 11 , wherein the first transistor is a silicon-oxide-nitride-oxide-silicon (SONOS) transistor.

15. An apparatus, comprising:

a first cell including a first control gate and a first select gate;

a second cell including a second control gate and a second select gate;

wherein,

the first and second cells are in a same row but different columns,

the first and second cells are coupled to a common source line,

the first and second cells share a first select gate line and a first control gate line,

the first select gate line, the first control gate lines, and the common source line extend in a same direction.

16. The apparatus of claim 15 , wherein the first select gate line, the first control gate line, and the common source line are disposed on a same level overlying a substrate.

17. The apparatus of claim 16 , wherein the common source line is electrically coupled to the first cell and the second cell via a first contact.

18. The apparatus of claim 16 , wherein the common source line is made of conductive metal or metal alloy.

19. The apparatus of claim 15 , wherein the common source line includes diffusion regions in a substrate providing a conductive path.

20. The apparatus of claim 15 , further comprising:

bit lines, each bit line being couple to cells of a same column, wherein the bit lines extend perpendicularly to the common source line.