Semiconductor packages and methods of forming the same

1. A device comprising:

a first device package comprising:

a first redistribution structure comprising a first redistribution line and a second redistribution line;

a die on the first redistribution structure;

a first via coupled to a first side of the first redistribution line;

a second via coupled to a first side of the second redistribution line and extending through the second redistribution line from the first side of the second redistribution line to a second side of the second redistribution line distal the first side of the second redistribution line;

an encapsulant surrounding the die, the first via, and the second via; and

a second redistribution structure over the encapsulant, the second redistribution structure electrically connected to the die, the first via, and the second via;

a first conductive connector coupled to a second side of the first redistribution line, the first conductive connector disposed along a different axis than a longitudinal axis of the first via; and

a second conductive connector coupled to a second side of the second redistribution line, the second conductive connector disposed along a longitudinal axis of the second via.

2. The device of claim 1 , further comprising:

a second device package comprising a first bond pad and a second bond pad, the first conductive connector coupled to the first bond pad, the second conductive connector coupled to the second bond pad.

3. The device of claim 2 , wherein the first bond pad and the second bond pad have a nickel finish.

4. The device of claim 2 , wherein the first redistribution line and the second redistribution line are formed from copper.

5. The device of claim 1 , wherein the first redistribution structure further comprises:

a first dielectric layer, the first redistribution line and the second redistribution line disposed on the first dielectric layer; and

a second dielectric layer on the first dielectric layer.

6. The device of claim 5 , wherein the second via is longer than the first via.

7. A method comprising:

forming a first redistribution structure comprising:

depositing a first dielectric layer over a carrier substrate;

forming a first conductive feature on the first dielectric layer;

forming a second conductive feature on the first dielectric layer;

forming a third conductive feature on the first dielectric layer; and

depositing a second dielectric layer on the first conductive feature, the second conductive feature, and the third conductive feature;

forming a first via on the first conductive feature;

forming a second via on the second conductive feature and on the third conductive feature, the second via extending between the second conductive feature and the third conductive feature;

attaching a die to the first redistribution structure adjacent the first via and the second via;

encapsulating the die, the first via, and the second via with an encapsulant;

planarizing the encapsulant, the first via, and the second via; and

forming a second redistribution structure over the encapsulant, the first via, the second via, and the die.

8. The method of claim 7 , further comprising:

debonding the carrier substrate from the first redistribution structure; and

attaching a device package to the first redistribution structure, the device package attached to the first conductive feature with a first connector, the device package attached to the second conductive feature and the third conductive feature with a second connector.

9. The method of claim 8 , wherein the first connector is not disposed along a longitudinal axis of the first via.

10. The method of claim 8 , wherein the second connector is disposed along a longitudinal axis of the second via.

11. The method of claim 7 , wherein the first via is longer than the second via after the planarizing.

12. A method comprising:

depositing a first seed layer on a first dielectric layer;

plating a first conductive feature and a second conductive feature on the first seed layer;

depositing a second dielectric layer on the first conductive feature and the second conductive feature;

forming a first opening in the second dielectric layer, the first opening exposing the first conductive feature, the second conductive feature, and the first dielectric layer;

depositing a second seed layer on the second dielectric layer and in the first opening;

plating a first via from portions of the second seed layer in the first opening;

attaching a die to the second dielectric layer; and

encapsulating the first via and the die with an encapsulant.

13. The method of claim 12 , further comprising:

forming a second opening in the first dielectric layer, the second opening exposing the first seed layer and the second seed layer;

etching exposed portions of the first seed layer and the second seed layer to remove at least a portion of the first seed layer and the second seed layer;

forming a reflowable material in the second opening, the reflowable material disposed along a longitudinal axis of the first via; and

reflowing the reflowable material to form an intermetallic compound from the reflowable material and conductive material of the first seed layer, the second seed layer, and the first via.

14. The method of claim 13 , further comprising:

attaching a device package to the first conductive feature and the second conductive feature with the reflowable material.

15. The method of claim 13 , wherein reflowing the reflowable material comprises diffusing portions of the conductive material of the first via into the reflowable material.

16. The method of claim 12 , further comprising:

forming a third conductive feature on the first dielectric layer;

depositing the second dielectric layer on the third conductive feature;

forming a second opening in the second dielectric layer, the second opening exposing the third conductive feature;

depositing the second seed layer in the second opening; and

plating a second via from portions of the second seed layer in the second opening.

17. The method of claim 16 , further comprising:

forming a third opening in the first dielectric layer, the third opening exposing the first seed layer;

etching exposed portions of the first seed layer to remove at least a portion of the first seed layer;

forming a reflowable material in the third opening, the reflowable material disposed along a different axis than a longitudinal axis of the second via; and

reflowing the reflowable material to form an intermetallic compound from the reflowable material and conductive material of the first seed layer.

18. The method of claim 17 , wherein reflowing the reflowable material comprises diffusing portions of the conductive material of the third conductive feature into the reflowable material.

19. The method of claim 17 , wherein no portion of the intermetallic compound is formed between the second via and the first dielectric layer.

20. The method of claim 16 , further comprising:

planarizing the first via, the second via, and the encapsulant, the first via being longer than the second via after the planarizing.