Fabrication of vertical fin transistor with multiple threshold voltages

1. A method of fabricating one or more vertical fin field effect transistors, comprising:

epitaxially growing a silicon-germanium vertical fin on a substrate;

forming a bottom spacer on the substrate adjacent to the silicon-germanium vertical fin;

forming a cap on a top surface of the silicon-germanium vertical fin, wherein sidewalls of the silicon-germanium vertical fin are exposed between the cap and the top surface of the bottom spacer layer;

oxidizing the sidewalls of the silicon-germanium vertical fin below the cap to form silicon oxide layers at least on opposite sides of the silicon-germanium vertical fin, and increasing the germanium concentration of the silicon-germanium vertical fin, wherein an area between the cap and the top surface of the silicon-germanium vertical fin is free of the silicon oxide layers;

removing the silicon oxide layers to form a portion of the silicon-germanium vertical fin having a reduced width, while maintaining the original height of the silicon-germanium vertical fin;

forming a source/drain in the substrate below the silicon-germanium vertical fin with the reduced width; and

exposing the top surface of the silicon-germanium vertical fin with the reduced width.

2. The method of claim 1 , wherein the silicon-germanium vertical fin with the reduced width has a germanium concentration in the range of about 20 at. % Ge to about 50 at. % Ge.

3. The method of claim 2 , further comprising, forming a gate structure on the sidewalls of the silicon-germanium vertical fin with the reduced width.

4. The method of claim 3 , wherein the silicon-germanium vertical fin with the reduced width has a reduced threshold voltage.

5. The method of claim 3 , wherein the gate structure includes a gate dielectric layer and a gate conductor layer.

6. The method of claim 5 , further comprising, forming a source/drain region on the top of the silicon-germanium vertical fin with the reduced width.

7. The method of claim 6 , wherein the source/drain region has the same crystal orientation as the silicon-germanium vertical fin with the reduced width.

8. The method of claim 7 , further comprising, forming a shallow trench isolation region adjacent to the silicon-germanium vertical fin with the reduced width.

9. The method of claim 8 , wherein the gate structure has a height in the range of about 10 nm to about 300 nm.

10. A method of fabricating one or more vertical fin field effect transistors, comprising:

epitaxially growing a silicon-germanium vertical fin on a single-crystal silicon substrate;

forming a bottom spacer on the substrate adjacent to the silicon-germanium vertical fin;

forming a cap on a top surface of the silicon-germanium vertical fin, wherein sidewalls of the silicon-germanium vertical fin are exposed between the cap and the top surface of the bottom spacer layer;

oxidizing the sidewalls of the silicon-germanium vertical fin to form silicon oxide layers at least on opposite sides of the silicon-germanium vertical fin, and increasing the germanium concentration of the silicon-germanium vertical fin, wherein an area between the cap and the top surface of the silicon-germanium vertical fin is free of the silicon oxide layers;

removing the silicon oxide layers to form a portion of the silicon-germanium vertical fin having a reduced width, while maintaining the original height of the silicon-germanium vertical fin;

forming a gate dielectric layer and a gate conductor layer on the silicon-germanium vertical fin having the reduced width, where the gate dielectric layer and a gate conductor layer surround the vertical fin having the reduced width; and

forming a source/drain in the substrate below the silicon-germanium vertical fin.

11. The method of claim 10 , wherein the gate dielectric layer and the gate conductor layer have a height in the range of about 10 nm to about 300 nm on the silicon-germanium vertical fin having a reduced width.

12. The method of claim 10 , wherein the material of the gate dielectric layer is selected from the group consisting of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), a high-K material, and combinations thereof.

13. The method of claim 10 , wherein the silicon-germanium vertical fin with the reduced width has a germanium concentration in the range of about 20 at. % Ge to about 50 at. % Ge.

14. The method of claim 10 , wherein the silicon-germanium vertical fin with the reduced width has a width in the range of about 5 nm to about 20 nm.

15. A method of fabricating one or more vertical fin field effect transistors, comprising:

epitaxially growing a silicon-germanium vertical fin on a single-crystal silicon substrate;

forming a cap on a top surface of the silicon-germanium vertical fin;

forming a bottom spacer on the substrate adjacent to the silicon-germanium vertical fin, wherein the bottom spacer has a height less than the height of the silicon-germanium vertical fin that covers a lower portion of sidewalls of the silicon-germanium vertical fin;

oxidizing an exposed portion of the sidewalls of the silicon-germanium vertical fin between the bottom spacer and the cap to form silicon oxide layers at least on opposite sides of the silicon-germanium vertical fin, and increasing the germanium concentration of the silicon-germanium vertical fin; and

removing the silicon oxide layers to form an upper portion of the silicon-germanium vertical fin having a reduced width;

forming a gate dielectric layer and a gate conductor layer on the silicon-germanium vertical fin having a reduced width;

forming a source/drain in the substrate below the silicon-germanium vertical fin with the reduced width;

removing the cap to expose the top surface of the silicon-germanium vertical fin with the reduced width; and

forming a source/drain region on the top surface of the silicon-germanium vertical fin with the reduced width.

16. The method of claim 15 , wherein the silicon-germanium vertical fin with the reduced width has a width in the range of about 7 nm to about 12 nm.

17. The method of claim 16 , wherein the silicon-germanium vertical fin with the reduced width has a germanium concentration in the range of about 30 at. % Ge to about 50 at. % Ge.

18. The method of claim 17 , wherein the gate dielectric layer and the gate conductor layer have a height in the range of about 15 nm to about 200 nm on the silicon-germanium vertical fin having a reduced width.

19. The method of claim 17 , wherein the source/drain region has the same crystal orientation as the silicon-germanium vertical fin with the reduced width.

20. The method of claim 19 , further comprising, forming a top spacer on the silicon-germanium vertical fin with the reduced width, wherein the top spacer electrically isolates the gate conductor layer from the source/drain region.