IP Library Granted Patent US 10,438,893
Granted Patent B2
US 10,438,893 · App. 15/784,180 · Granted Oct 8, 2019

Metal interconnect structure and method for fabricating the same

Inventors: Shih-Hsien Chen (Kaohsiung, TW); Meng-Jun Wang (Taichung, TW); Ting-Chun Wang (New Taipei, TW); Chih-Sheng Chang (Tainan, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L23/53295H01L21/02115H01L21/31116H01L21/31144H01L21/7682H01L21/7685H01L21/76828H01L21/76832H01L21/76895H01L23/528H01L23/5222H01L23/53228
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Quick Facts
Patent No.
US 10,438,893
App. No.
15/784,180
Granted
Oct 8, 2019
Kind
B2
Abstract

A method for fabricating semiconductor device includes the steps of: providing a substrate having a first inter-metal dielectric (IMD) layer thereon; forming a first metal interconnection and a second metal interconnection in the first IMD layer; removing part of the first IMD layer to form a recess between the first metal interconnection and the second metal interconnection; performing a curing process; and forming a second IMD layer on the first metal interconnection and the second metal interconnection.

Claims (22)

1. A method for fabricating semiconductor device, comprising: providing a substrate having a first inter-metal dielectric (IMD) layer thereon; forming a first metal interconnection and a second metal interconnection in the first IMD layer; forming a first cap layer on the first IMD layer, the first metal interconnection, and the second metal interconnection; performing an etching process to remove part of the first cap layer and part of the first IMD layer to form a recess between the first metal interconnection and the second metal interconnection; performing a curing process after removing part of the first IMD layer to form the recess; forming a second cap layer on the first metal interconnection and the second metal interconnection; and forming a second IMD layer after performing the curing process on the first metal interconnection, the second metal interconnection, and the second cap layer while forming an air gap; forming the air gap to have a bottom surface in direct contact with the second cap layer.

2. The method of claim 1 , wherein the first cap layer and the second cap layer comprise same material.

3. The method of claim 2 , wherein the first cap layer and the second cap layer comprise nitrogen doped carbide (NDC).

4. The method of claim 1 , wherein the first cap layer and the second cap layer comprise different material.

5. The method of claim 4 , wherein the first cap layer comprises nitrogen doped carbide (NDC) and the second cap layer comprises metal nitride.

6. The method of claim 1 , wherein the air gap is enclosed by the second cap layer and the second IMD layer.

7. The method of claim 1 , wherein a vertex of the air gap is higher than a top surface of the first metal interconnection.

8. The method of claim 1 , wherein the top surfaces of the first metal interconnection and the first IMD layer are coplanar.

9. The method of claim 1 , wherein a temperature of the curing process is between 347° C. to 424° C.

10. A semiconductor device, comprising:

a substrate having a first inter-metal dielectric (IMD) layer thereon;

a first metal interconnection and a second metal interconnection in the first IMD layer;

a first cap layer on the first IMD layer;

a second cap layer on the first metal interconnection and the second metal interconnection;

a second IMD layer on the second cap layer; and

an air gap between the first metal interconnection and the second metal interconnection, and the air gap is located within each of the second IMD layer and the second cap layer, wherein the air gap extends from the second cap layer into the second IMD layer, wherein a vertex of the air gap is higher than a top surface of the first metal interconnection and a bottom surface of the air gap contacts the second cap layer directly.

11. The semiconductor device of claim 10 , wherein the first cap layer and the second cap layer comprise same material.

12. The semiconductor device of claim 11 , wherein the first cap layer and the second cap layer comprise nitrogen doped carbide (NDC).

13. The semiconductor device of claim 10 , wherein the first cap layer and the second cap layer comprise different material.

14. The semiconductor device of claim 13 , wherein the first cap layer comprises nitrogen doped carbide (NDC) and the second cap layer comprises metal nitride.

15. The semiconductor device of claim 10 , wherein a bottom surface of the air gap is lower than half the height of the first metal interconnection.

16. The semiconductor device of claim 10 , wherein the top surfaces of the first metal interconnection and the first IMD layer are coplanar.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2021
From: UNITED MICROELECTRONICS CORPORATION
To: MARLIN SEMICONDUCTOR LIMITED
Reel/Frame 056991/0292 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 15, 2017
From: CHEN, SHIH-HSIEN; WANG, MENG-JUN; WANG, TING-CHUN; CHANG, CHIH-SHENG
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 043866/0716 →