Semiconductor package and method of manufacturing the semiconductor package

1. A semiconductor package, comprising:

a package substrate having an upper surface and a lower surface and including a plurality of substrate pads formed on the upper surface;

a capacitor structure arranged on the upper surface of the package substrate and including a semiconductor substrate and at least one decoupling capacitor formed in an upper region of the semiconductor substrate;

a plurality of first semiconductor chips mounted on the package substrate and supported by the capacitor structure;

a second semiconductor chip arranged on the upper surface of the package substrate, the second semiconductor chip being spaced apart from the capacitor structure;

first conductive connection members electrically connecting chip pads of the first semiconductor chips to the plurality of substrate pads; and

second conductive connection members electrically connecting capacitor pads of the at least one decoupling capacitor to the plurality of substrate pads,

wherein a thickness of the second semiconductor chip is the same as a thickness of the capacitor structure,

wherein the first semiconductor chips are mounted on the capacitor structure and the second semiconductor chip using an adhesive film that is in contact with the capacitor structure and the second semiconductor chip,

wherein the at least one decoupling capacitor is a plurality of decoupling capacitors each including respective capacitor pads, the plurality of decoupling capacitors are formed on the semiconductor substrate to be electrically isolated from each other, and the plurality of decoupling capacitors are electrically connected to the respective capacitor pads, and

wherein the second conductive connection members include bonding wires that electrically connect the respective capacitor pads to the respective substrate pads.

2. The semiconductor package of claim 1 , wherein the decoupling capacitor comprises at least one of a metal-oxide-semiconductor type capacitor, a cell type capacitor and a metal wiring type capacitor formed on the semiconductor substrate.

3. The semiconductor package of claim 1 , wherein a subset of the plurality of decoupling capacitors are electrically connected to the package substrate.

4. The semiconductor package of claim 1 , wherein the capacitor structure has a height of from about 10 μm to about 800 μm.

5. The semiconductor package of claim 1 , wherein the capacitor pads are provided on an upper surface of the capacitor structure.

6. The semiconductor package of claim 1 , wherein the first conductive connection members include bonding wires.

7. A semiconductor package, comprising:

a package substrate;

a first semiconductor chip mounted on the package substrate;

a capacitor structure arranged on the package substrate to be spaced apart from the first semiconductor chip and including a semiconductor substrate and at least one decoupling capacitor formed in an upper surface of the semiconductor substrate;

a plurality of second semiconductor chips mounted on the capacitor structure and the first semiconductor chip using an adhesive film that is in contact with the capacitor structure and the first semiconductor chip and supported by the capacitor structure and the first semiconductor chip; and

conductive connection members electrically connecting capacitor pads of the at least one decoupling capacitor to a substrate pad of the package substrate,

wherein a thickness of the first semiconductor chip is the same as a thickness of the capacitor structure,

wherein the at least one decoupling capacitor is a plurality of decoupling capacitors each including respective capacitor pads, the plurality of decoupling capacitors are formed on the semiconductor substrate to be isolated from each other, and the plurality of decoupling capacitors are electrically connected to the respective capacitor pads, and

wherein the conductive connection members include bonding wires that electrically connect the respective capacitor pads to the respective substrate pads.

8. The semiconductor package of claim 7 , wherein the decoupling capacitor comprises at least one of a metal-oxide-semiconductor type capacitor, a cell type capacitor and a metal wiring type capacitor formed on the semiconductor substrate.

9. The semiconductor package of claim 7 , wherein:

the first semiconductor chip is one of a plurality of first semiconductor chips stacked on the package substrate,

wherein the plurality of first semiconductor chips are positioned between the package substrate and a lowermost second semiconductor chip of the plurality of the second semiconductor chips.

10. A semiconductor package, comprising:

a package substrate having an upper surface and including a plurality of substrate pads formed on the upper surface;

a capacitor structure arranged on the upper surface of the package substrate and including a semiconductor substrate and at least one decoupling capacitor formed in an upper surface of the semiconductor substrate;

a first semiconductor chip mounted on the package substrate to be spaced apart from the capacitor structure;

a plurality of second semiconductor chips mounted on the capacitor structure and the first semiconductor chip and supported by the capacitor structure and the first semiconductor chip;

first conductive connection members electrically connecting first chip pads of the first semiconductor chip to the plurality of substrate pads;

second conductive connection members electrically connecting second chip pads of the plurality of second semiconductor chips to the plurality of substrate pads; and

third conductive connection members electrically connecting capacitor pads of the at least one decoupling capacitor to the plurality of substrate pads,

wherein an upper surface of the capacitor structure is at a same vertical level as an upper surface of the first semiconductor chip,

wherein a lower surface of the capacitor structure is at a same vertical level as a lower surface of the first semiconductor chip,

wherein the at least one decoupling capacitor is a plurality of decoupling capacitors each including respective capacitor pads, the plurality of decoupling capacitors are formed on the semiconductor substrate to be electrically isolated from each other, and the plurality of decoupling capacitors are electrically connected to the respective capacitor pads, and

wherein the third conductive connection members include bonding wires that electrically connect the respective capacitor pads to the respective substrate pads.

11. The semiconductor package of claim 10 , wherein a thickness of the first semiconductor chip is the same as a thickness of the capacitor structure.

12. The semiconductor package of claim 10 , further including:

a third semiconductor chip arranged on the upper surface of the package substrate, the third semiconductor chip being spaced apart from the capacitor structure and the first semiconductor chip.

13. The semiconductor package of claim 12 , wherein a thickness of the third semiconductor chip is the same as a thickness of the capacitor structure and the same as a thickness of the first semiconductor chip.