IP Library Granted Patent US 10,056,317
Granted Patent B1
US 10,056,317 · App. 15/789,120 · Granted Aug 21, 2018

Semiconductor package with grounding device and related methods

Inventors: Atapol Prajuckamol (Klaeng, TH); Sw Wang (Seremban, MY); Kai Chat Tan (Tangkak, MY)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01L23/4951H01L23/4952H01L23/49861H01L24/03
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Quick Facts
Patent No.
US 10,056,317
App. No.
15/789,120
Granted
Aug 21, 2018
Kind
B1
Abstract

Implementations of a semiconductor package may include a first side of a die coupled to a first side of an electrically insulative layer, a second side of the electrically insulative layer coupled to a lead frame, and at least one ground stud physically coupled to the lead frame and to the die, the at least one ground stud extending from the second side of the electrically insulative layer into the electrically insulative layer from the lead frame. The die may be wire bonded to the lead frame.

Claims (35)

1. A semiconductor package comprising:

a first side of a die coupled to a first side of an electrically insulative layer;

a second side of the electrically insulative layer coupled to a lead frame; and

at least one ground stud physically coupled to the lead frame and to the die, the at least one ground stud extending from the second side of the electrically insulative layer into the electrically insulative layer from the lead frame;

wherein the die is wire bonded to the lead frame.

2. The package of claim 1 , further comprising an electrically conductive layer coupled between the electrically insulative layer and the die.

3. The package of claim 1 , wherein the at least one ground stud comprises two ground studs physically coupled to the lead frame and the die.

4. The package of claim 1 , wherein the at least one ground stud extends completely through the electrically insulative layer.

5. The package of claim 1 , wherein the lead frame comprises a die flag coupled to the second side of the electrically insulative layer.

6. The package of claim 5 , wherein the at least one ground stud physically contacts the die flag and is physically coupled to the die.

7. The package of claim 1 , wherein the semiconductor package is a chip on lead package.

8. A semiconductor package comprising:

a first side of a die directly coupled to a first side of an electrically conductive layer;

a first side of an electrically non-conductive layer directly coupled to a second side of the electrically conductive layer opposing the first side of the electrically conductive layer;

a lead frame directly coupled to a second side of the electrically non-conductive layer opposing a first side of the electrically non-conductive layer; and

at least one ground stud coupled to the lead frame, wherein the ground stud extends through the electrically non-conductive layer and into the electrically conductive layer physically coupling the lead frame and the second side of the electrically conductive layer together;

wherein a second side of the die is wire bonded to the lead frame.

9. The package of claim 8 , wherein the at least one ground stud comprises two ground studs physically coupled to the lead frame and the die.

10. The package of claim 8 , wherein the electrically conductive layer is a first wafer backside coating.

11. The package of claim 8 , wherein the electrically non-conductive layer is a second wafer backside coating.

12. The package of claim 8 , wherein the at least one ground stud is 35-40 micrometers thick.

13. The package of claim 8 , wherein the lead frame comprises a die flag coupled to the second side of the electrically non-conductive layer.

14. The package of claim 13 , wherein the at least one ground stud physically contacts the die flag and is physically coupled to the die.

15. A method of forming a semiconductor package comprising:

coating a wafer with a first wafer backside coating (WBC);

forming a second WBC over the first WBC;

singulating the wafer into a plurality of die;

forming at least one ground stud on a lead frame;

pressing the at least one ground stud through a material of the second WBC to contact the at least one ground stud with the first WBC; and

wirebonding the die to the lead frame.

16. The method of claim 15 , wherein the first WBC is electrically conductive.

17. The method of claim 15 , wherein the second WBC is electrically non-conductive.

18. The method of claim 15 , wherein the at least one ground stud comprises two ground studs physically coupled to the lead frame and the die.

19. The method of claim 15 , wherein the at least one ground stud is gold.

20. The method of claim 15 , wherein the at least one ground stud is copper.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 046530, FRAME 0494 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064159/0524 →
PATENT SECURITY AGREEMENT Recorded Jul 11, 2018
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 046530/0494 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 20, 2017
From: PRAJUCKAMOL, ATAPOL; WANG, SW; TAN, KAI CHAT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 043911/0674 →