Semiconductor chip

1. A semiconductor chip comprising:

a semiconductor substrate including a bump region, a non-bump region, and a dummy region between the bump region and the non-bump region;

a dummy pattern on the dummy region;

a bump on the bump region, the non-bump region having no bump; and

a passivation layer on the bump region, the dummy region, and the non-bump region of the semiconductor substrate,

a thickness of the passivation layer at the bump region being thicker than a thickness of the passivation layer at the non-bump region,

the passivation layer covering the dummy pattern and insulating the dummy pattern, and

the passivation layer including a step between the bump region and the non-bump region, the step defined by an upper surface of the passivation layer at a portion of the passivation layer that protrudes upward over a boundary between the dummy region and the non-bump region.

2. The semiconductor chip of claim 1 , further comprising:

a lower passivation layer below the passivation layer, wherein

the passivation layer is an upper passivation layer, and

the dummy pattern is between the lower passivation layer and the upper passivation layer.

3. The semiconductor chip of claim 1 , wherein

the passivation layer includes one of an oxide layer, a nitride layer, or a photo-sensitive organic layer.

4. The semiconductor chip of claim 1 , wherein

the bump region extends a distance from opposite side walls of the bump in a horizontal direction.

5. The semiconductor chip of claim 1 , further comprising:

a barrier metal pad on the bump region, wherein

the bump is on the barrier metal pad.

6. The semiconductor chip of claim 1 , further comprising:

a bump pad on the bump region; and

a barrier metal pad on the bump pad, wherein

the bump is on the barrier metal pad.

7. The semiconductor chip of claim 1 , wherein the passivation layer includes a recess portion in the non-bump region.

8. The semiconductor chip of claim 1 , wherein

the semiconductor substrate includes a first surface and a second surface opposite the first surface, and one of the first surface or the second surface of the semiconductor substrate includes an active region.

9. The semiconductor chip of claim 1 , further comprising:

a plurality of bumps that are spaced apart from one another on the bump region of the semiconductor substrate, wherein

the plurality of bumps include the bump, and

the thickness of the passivation layer surrounding some of the plurality of bumps is thicker than the thickness of the passivation layer in the non-bump region.

10. The semiconductor chip of claim 1 , further comprising:

a plurality of bumps that are spaced apart from one another on the bump region of the semiconductor substrate, wherein

the semiconductor substrate includes a center region and a peripheral region isolated from the center region and surrounding the center region, and

the thickness of the passivation layer surrounding some or all of the plurality of bumps in the center region is thicker than the thickness of the passivation layer in the non-bump region.

11. The semiconductor chip of claim 1 , further comprising:

a plurality of bumps that are spaced apart from one another on the bump region of the semiconductor substrate, wherein

an upper surface of the semiconductor substrate includes a plurality of sub-regions that are isolated from one another in a direction from a first side to a second side of the semiconductor substrate, and

the thickness of the passivation layer surrounding some or all of the plurality of bumps in at least one of the sub-regions is thicker than the thickness of the passivation layer in the non-bump region.

12. The semiconductor chip of claim 1 , further comprising:

a via in the bump region.

13. A semiconductor chip comprising:

a semiconductor substrate including a first surface opposite a second surface,

the semiconductor substrate including a bump region, a non-bump region, a redistribution wiring region, and a dummy region;

a bump pad on the first surface of the semiconductor substrate in the bump region;

a bump on the bump pad, the non-bump region having no bump;

at least one of a redistribution wiring pattern on the redistribution wiring region and a dummy pattern on the dummy region, the at least one of the redistribution wiring pattern and the dummy pattern being on the first surface or the second surface of the semiconductor substrate; and

a passivation layer covering the bump region, the non-bump region, the redistribution wiring region, and the dummy region on the first surface or the second surface of the semiconductor substrate,

a thickness of the passivation layer at the bump region being thicker than a thickness of the passivation layer at the non-bump region, and

the passivation layer including a first step between the bump region and the non-bump region, the first step defined by an upper surface of the passivation layer at a portion that protrudes upward over a boundary between the dummy region and the non-bump region.

14. The semiconductor chip of claim 13 , wherein

a thickness of redistribution wiring pattern and the dummy pattern is equal to a thickness of the bump pad, and

the passivation layer covers the redistribution wiring pattern and the dummy pattern.

15. The semiconductor chip of claim 13 , wherein

a thickness of the passivation layer in the redistribution wiring region and the dummy region is thicker than a thickness of the passivation layer in the non-bump region, and

the passivation layer includes a second step between the non-bump region and the bump region, the second step defined by a part of the passivation layer over a boundary between the non-bump region and the bump region.

16. A semiconductor chip comprising:

a semiconductor substrate including a first surface opposite a second surface;

a bump connected to one of the first surface and the second surface;

a redistribution pattern on the semiconductor substrate, the redistribution pattern being spaced apart from the bump; and

a passivation layer on the semiconductor substrate and extending along the one of the first surface and the second surface of the semiconductor substrate,

the passivation layer including a first portion having a first thickness, a second portion having a second thickness that is less than the first thickness, and a step defining the first portion and the second portion,

the first portion of the passivation layer covering the redistribution pattern,

the step defined by an upper surface of the passivation layer at a portion that protrudes upward,

the first portion of the passivation layer extending along an upper surface and a side surface of the redistribution pattern, and

the first portion of the passivation layer defining a hole between the bump and the semiconductor substrate.

17. The semiconductor chip of claim 16 , wherein

the bump is a connection terminal for electrically connecting the semiconductor chip to another semiconductor chip or an external semiconductor chip, and

no bump is on a portion of the semiconductor substrate covered by the second portion of the passivation layer.

18. The semiconductor chip of claim 16 , further comprising:

a lower passivation layer between the passivation layer and the semiconductor substrate, wherein

a thickness of the lower passivation layer is the same along the first portion of passivation layer and the second portion of the passivation layer, and

the passivation layer is an upper passivation layer.

19. The semiconductor chip of claim 18 , wherein

the lower passivation layer includes at least one of an oxide layer and a nitride layer, and

the upper passivation layer includes at least one oxide layer, a nitride layer, and an organic layer.

20. The semiconductor chip of claim 16 , further comprising:

a via extending through the semiconductor substrate; and

at least one of a bump pad and a barrier metal pad on the via, wherein

the bump is electrically connected to the via through the at least one of the bump pad and the barrier metal pad.