Configurable computing array using two-sided integration
View Patent ↗The present invention discloses a configurable computing array using two-sided integration. It is a monolithic integrated circuit comprising at least a configurable computing element located on one side of the substrate and at least a configurable logic element on the other side of the substrate. Each configurable computing element comprises at least a writable-memory array, which stores at least a portion of a look-up table (LUT) for a math function.
1. A configurable computing-array die, comprising:
a semiconductor substrate having a first side and a second side;
an array of configurable computing elements including first and second configurable computing elements disposed on said first side of said semiconductor substrate, wherein said first configurable computing element comprises a first memory for storing a first look-up table (LUT) for a first math function; and, said second configurable computing element comprises a second memory for storing a second LUT for a second math function;
an array of configurable logic elements including a configurable logic element disposed on said second side of said semiconductor substrate, wherein said configurable logic element selectively realizes a logic function from a logic library;
a plurality of through-substrate vias through said semiconductor substrate for coupling said configurable computing elements and said configurable logic elements;
whereby said configurable computing-array die realizes a complex math function by programming said configurable computing elements and said configurable logic elements, wherein said complex math function is a combination of at least said first and second math functions.
2. The configurable computing-array die according to claim 1 , wherein:
said first side is a front side of said semiconductor substrate; and,
said second side is a back side of said semiconductor substrate.
3. The configurable computing-array die according to claim 1 , wherein:
said first side is a back side of said semiconductor substrate; and,
said second side is a front side of said semiconductor substrate.
4. The configurable computing-array die according to claim 1 , wherein said through-substrate vias are through-silicon vias (TSV).
5. The configurable computing-array die according to claim 1 , further comprising an array of configurable interconnects including a configurable interconnect, wherein said configurable interconnect selectively realizes an interconnect from an interconnect library.
6. The configurable computing-array die according to claim 5 , wherein selected ones of said configurable interconnects are located on said first side.
7. The configurable computing-array die according to claim 5 , wherein selected ones of said configurable interconnects are located on said second side.
8. The configurable computing-array die according to claim 5 , wherein said configurable interconnects are located on said first and second sides.
9. The configurable computing-array die according to claim 1 , wherein each of said configurable computing elements comprises a re-programmable memory, whereby each of said configurable computing elements can be re-configured to realize a different math function by loading the LUT for said different math function into said re-programmable memory.
10. The configurable computing-array die according to claim 1 , further comprising at least one multiplier.
11. A configurable computing-array die, comprising:
a semiconductor substrate having a first side and a second side;
an array of configurable computing elements including first and second configurable computing elements disposed on said first side of said semiconductor substrate, wherein said first configurable computing element comprises a first memory for storing a first look-up table (LUT) for a first math function; and, said second configurable computing element comprises a second memory for storing a second LUT for a second math function;
an array of configurable logic elements including a configurable logic element disposed on said second side of said semiconductor substrate, wherein said configurable logic element selectively realizes a logic function from a logic library;
an array of configurable interconnects including a configurable interconnect, wherein said configurable interconnect selectively realizes an interconnect from an interconnect library;
a plurality of through-substrate vias through said semiconductor substrate for coupling said configurable computing elements and said configurable logic elements;
whereby said configurable computing-array die realizes a complex math function by programming said configurable computing elements, said configurable logic elements and said configurable interconnects, wherein said complex math function is a combination of at least said first and second math functions.
12. The configurable computing-array die according to claim 11 , wherein:
said first side is a front side of said semiconductor substrate; and,
said second side is a back side of said semiconductor substrate.
13. The configurable computing-array die according to claim 11 , wherein:
said first side is a back side of said semiconductor substrate; and,
said second side is a front side of said semiconductor substrate.
14. The configurable computing-array die according to claim 11 , wherein said through-substrate vias are through-silicon vias (TSV).
15. The configurable computing-array die according to claim 11 , wherein selected ones of said configurable interconnects are located on said first side.
16. The configurable computing-array die according to claim 11 , wherein selected ones of said configurable interconnects are located on said second side.
17. The configurable computing-array die according to claim 11 , wherein said configurable interconnects are located on said first and second sides.
18. The configurable computing-array die according to claim 11 , wherein each of said configurable computing elements comprises a re-programmable memory, whereby each of said configurable computing elements can be re-configured to realize a different math function by loading the LUT for said different math function into said re-programmable memory.
19. The configurable computing-array die according to claim 18 , wherein the usage cycle of said configurable computing elements includes:
a configuration stage during which the LUT for a math function is loaded into said re-programmable memory;
a computation stage during which a selected portion of the LUT for said math function is read out from said re-programmable memory.
20. The configurable computing-array die according to claim 11 , further comprising at least one multiplier.